From: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
Date: Mon, 8 Aug 2022 06:46:00 +0000 (+0530)
Subject: spi: dt-binding: document microchip coreQSPI
X-Git-Tag: microblaze-v6.2~178^2~55^2~3
X-Git-Url: http://git.monstr.eu/?a=commitdiff_plain;h=a5890c12ecce2696f90ef7d2b8fbb33387f735de;p=linux-2.6-microblaze.git

spi: dt-binding: document microchip coreQSPI

Add microchip coreQSPI compatible string and update the title/description
to reflect this addition.

Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220808064603.1174906-2-nagasuresh.relli@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---

diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
index 7326c0a28d16..a47d4923b51b 100644
--- a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
@@ -4,7 +4,11 @@
 $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Microchip MPFS {Q,}SPI Controller Device Tree Bindings
+title: Microchip FPGA {Q,}SPI Controllers
+
+description:
+  SPI and QSPI controllers on Microchip PolarFire SoC and the "soft"/
+  fabric IP cores they are based on
 
 maintainers:
   - Conor Dooley <conor.dooley@microchip.com>
@@ -17,6 +21,7 @@ properties:
     enum:
       - microchip,mpfs-spi
       - microchip,mpfs-qspi
+      - microchip,coreqspi-rtl-v2 # FPGA QSPI
 
   reg:
     maxItems: 1