From: Angelo Dureghello Date: Mon, 28 Oct 2024 21:45:28 +0000 (+0100) Subject: dt-bindings: iio: dac: ad3552r: add iio backend support X-Git-Tag: microblaze-v6.16~492^2~11^2~56 X-Git-Url: http://git.monstr.eu/?a=commitdiff_plain;h=76830926323ef2f7f337fa6a7f6a19c365efa01c;p=linux-2.6-microblaze.git dt-bindings: iio: dac: ad3552r: add iio backend support There is a version of AXI DAC IP block (for FPGAs) that provides a physical QSPI bus for AD3552R and similar chips, so supporting spi-controller functionalities. For this case, the binding is modified to include some additional properties. Reviewed-by: Rob Herring (Arm) Acked-by: Conor Dooley Signed-off-by: Angelo Dureghello Reviewed-by: David Lechner Link: https://patch.msgid.link/20241028-wip-bl-ad3552r-axi-v0-iio-testing-v9-1-f6960b4f9719@kernel-space.org Signed-off-by: Jonathan Cameron --- diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml index 41fe00034742..2d2561a52683 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad3552r.yaml @@ -60,6 +60,12 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2, 3] + io-backends: + description: The iio backend reference. + Device can be optionally connected to the "axi-ad3552r IP" fpga-based + QSPI + DDR (Double Data Rate) controller to reach high speed transfers. + maxItems: 1 + '#address-cells': const: 1 @@ -128,6 +134,7 @@ patternProperties: - custom-output-range-config allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# - if: properties: compatible: