From: Grygorii Strashko Date: Tue, 3 Mar 2020 16:00:26 +0000 (+0200) Subject: dt-bindings: phy: ti: gmii-sel: add support for am654x/j721e soc X-Git-Tag: microblaze-v5.10~1183^2~13^2~10 X-Git-Url: http://git.monstr.eu/?a=commitdiff_plain;h=74e29703a78c120cd129e2b49ac8213713d2648c;p=linux-2.6-microblaze.git dt-bindings: phy: ti: gmii-sel: add support for am654x/j721e soc TI AM654x/J721E SoCs have the same PHY interface selection mechanism for CPSWx subsystem as TI SoCs (AM3/4/5/DRA7), but registers and bit-fields placement is different. This patch adds corresponding compatible strings to enable support for TI AM654x/J721E SoCs. Signed-off-by: Grygorii Strashko Acked-by: Rob Herring Signed-off-by: Kishon Vijay Abraham I --- diff --git a/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt b/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt index 50ce9ae0f7a5..83b78c1c0644 100644 --- a/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt +++ b/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt @@ -40,6 +40,7 @@ Required properties: "ti,dra7xx-phy-gmii-sel" for dra7xx/am57xx platform "ti,am43xx-phy-gmii-sel" for am43xx platform "ti,dm814-phy-gmii-sel" for dm814x platform + "ti,am654-phy-gmii-sel" for AM654x/J721E platform - reg : Address and length of the register set for the device - #phy-cells : must be 2. cell 1 - CPSW port number (starting from 1)