From: Evan Quan <evan.quan@amd.com>
Date: Fri, 25 Sep 2020 06:10:21 +0000 (+0800)
Subject: drm/amd/pm: correct VRconfig setting
X-Git-Tag: microblaze-v5.12~209^2~12^2~143
X-Git-Url: http://git.monstr.eu/?a=commitdiff_plain;h=55411d16233ed1a297e776210bb73d04b4753049;p=linux-2.6-microblaze.git

drm/amd/pm: correct VRconfig setting

Correct Polaris VRconfig setting.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
index 72ca4bd2c2f3..997b996b25bf 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
@@ -1712,6 +1712,9 @@ static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
 	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
 		config = VR_SVI2_PLANE_1;
 		table->VRConfig |= config;
+	} else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
+		config = VR_SMIO_PATTERN_1;
+		table->VRConfig |= config;
 	} else {
 		PP_ASSERT_WITH_CODE(false,
 				"VDDC should be on SVI2 control in merged mode!",
@@ -1730,7 +1733,17 @@ static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
 	}
 	/* Set Mvdd Voltage Controller */
 	if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
-		config = VR_SVI2_PLANE_2;
+		if (config != VR_SVI2_PLANE_2) {
+			config = VR_SVI2_PLANE_2;
+			table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
+			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
+				offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
+		} else {
+			config = VR_STATIC_VOLTAGE;
+			table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
+		}
+	} else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
+		config = VR_SMIO_PATTERN_2;
 		table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
 			offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);