From: Peter Zijlstra Date: Fri, 22 Oct 2021 15:49:53 +0000 (+0200) Subject: sched,x86: Fix L2 cache mask X-Git-Tag: microblaze-v5.18~673^2~6 X-Git-Url: http://git.monstr.eu/?a=commitdiff_plain;h=55409ac5c371c6403012d5f4df5e7c6cf0e7dce6;p=linux-2.6-microblaze.git sched,x86: Fix L2 cache mask Currently AMD/Hygon do not populate l2c_id, this means that for SMT enabled systems they report an L2 per thread. This is ofcourse not true but was harmless so far. However, since commit: 66558b730f25 ("sched: Add cluster scheduler level for x86") the scheduler topology setup requires: SMT <= L2 <= LLC Which leads to noisy warnings and possibly weird behaviour on affected chips. Therefore change the topology generation such that if l2c_id is not populated it follows the SMT topology, thereby satisfying the constraint. Fixes: 66558b730f25 ("sched: Add cluster scheduler level for x86") Reported-by: Tom Lendacky Signed-off-by: Peter Zijlstra (Intel) Tested-by: Tom Lendacky --- diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 5094ab0bae58..f80f4595ed41 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -470,9 +470,9 @@ static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) { int cpu1 = c->cpu_index, cpu2 = o->cpu_index; - /* Do not match if we do not have a valid APICID for cpu: */ + /* If the arch didn't set up l2c_id, fall back to SMT */ if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID) - return false; + return match_smt(c, o); /* Do not match if L2 cache id does not match: */ if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2))