From: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Date: Mon, 24 Jun 2019 10:52:24 +0000 (+0200)
Subject: arm64: dts: renesas: r8a77995: Add cpg reset for DU
X-Git-Tag: microblaze-v5.5-rc1~213^2~34^2~21
X-Git-Url: http://git.monstr.eu/?a=commitdiff_plain;h=3ed1db9071fde0ba9c4ce22a9b404887c0dbe909;p=linux-2.6-microblaze.git

arm64: dts: renesas: r8a77995: Add cpg reset for DU

Add CPG reset properties to DU node of D3 (r8a77995) SoC.

According to Laurent Pinchart, R-Car Gen3 reset is handled at the group
level so specifying one reset entry per group is sufficient.

This patch was inspired by a patch in the BSP by
Takeshi Kihara <takeshi.kihara.df@renesas.com>.

Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index 0a344eb55094..ca6aeabd6d04 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -1001,6 +1001,8 @@
 			clocks = <&cpg CPG_MOD 724>,
 				 <&cpg CPG_MOD 723>;
 			clock-names = "du.0", "du.1";
+			resets = <&cpg 724>;
+			reset-names = "du.0";
 			vsps = <&vspd0 0 &vspd1 0>;
 			status = "disabled";