From: Wei Li Date: Fri, 24 Jul 2020 07:11:11 +0000 (+0800) Subject: perf tools: No need to cache the PMUs in ARM SPE auxtrace init routine X-Git-Tag: microblaze-v5.10~67^2~67 X-Git-Url: http://git.monstr.eu/?a=commitdiff_plain;h=3e43d79da1dc9731aee24d8b3e8059a4d2297bfc;p=linux-2.6-microblaze.git perf tools: No need to cache the PMUs in ARM SPE auxtrace init routine - auxtrace_record__init() is called only once, so there is no point in using a static variable to cache the results of find_all_arm_spe_pmus(), make it local and free the results after use. - Another reason is, even though SPE is micro-architecture dependent, but so far it only supports "statistical-profiling-extension-v1" and we have no chance to use multiple SPE's PMU events in Perf command. So remove the useless check code to make it clear. Signed-off-by: Wei Li Reviewed-by: Mathieu Poirier Cc: Alexander Shishkin Cc: Hanjun Guo Cc: Jiri Olsa Cc: Kim Phillips Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Suzuki Poulouse Cc: linux-arm-kernel@lists.infradead.org Link: http://lore.kernel.org/lkml/20200724071111.35593-3-liwei391@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- diff --git a/tools/perf/arch/arm/util/auxtrace.c b/tools/perf/arch/arm/util/auxtrace.c index 28a5d0c18b1d..b187bddbd01a 100644 --- a/tools/perf/arch/arm/util/auxtrace.c +++ b/tools/perf/arch/arm/util/auxtrace.c @@ -57,17 +57,15 @@ struct auxtrace_record struct evsel *evsel; bool found_etm = false; struct perf_pmu *found_spe = NULL; - static struct perf_pmu **arm_spe_pmus = NULL; - static int nr_spes = 0; + struct perf_pmu **arm_spe_pmus = NULL; + int nr_spes = 0; int i = 0; if (!evlist) return NULL; cs_etm_pmu = perf_pmu__find(CORESIGHT_ETM_PMU_NAME); - - if (!arm_spe_pmus) - arm_spe_pmus = find_all_arm_spe_pmus(&nr_spes, err); + arm_spe_pmus = find_all_arm_spe_pmus(&nr_spes, err); evlist__for_each_entry(evlist, evsel) { if (cs_etm_pmu && @@ -84,6 +82,7 @@ struct auxtrace_record } } } + free(arm_spe_pmus); if (found_etm && found_spe) { pr_err("Concurrent ARM Coresight ETM and SPE operation not currently supported\n");