From: Alexandre Ghiti Date: Tue, 18 Mar 2025 11:52:54 +0000 (+0000) Subject: Merge patch series "riscv: Add bfloat16 instruction support" X-Git-Url: http://git.monstr.eu/?a=commitdiff_plain;h=2f2cd9f33435834a6dfca406bb121ff9a885fb23;p=linux-2.6-microblaze.git Merge patch series "riscv: Add bfloat16 instruction support" Inochi Amaoto says: Add description for the BFloat16 precision Floating-Point ISA extension, (Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62 ("Added Chapter title to BF16") of the riscv-isa-manual. * patches from https://lore.kernel.org/r/20250213003849.147358-1-inochiama@gmail.com: riscv: hwprobe: export bfloat16 ISA extension riscv: add ISA extension parsing for bfloat16 ISA extension dt-bindings: riscv: add bfloat16 ISA extension description Signed-off-by: Alexandre Ghiti Link: https://lore.kernel.org/r/20250213003849.147358-1-inochiama@gmail.com --- 2f2cd9f33435834a6dfca406bb121ff9a885fb23 diff --cc arch/riscv/include/uapi/asm/hwprobe.h index 8cac35cb19d8,aecc1c800d54..08ab52fe8004 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@@ -73,8 -73,9 +73,11 @@@ struct riscv_hwprobe #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47) #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48) #define RISCV_HWPROBE_EXT_SUPM (1ULL << 49) -#define RISCV_HWPROBE_EXT_ZFBFMIN (1ULL << 50) -#define RISCV_HWPROBE_EXT_ZVFBFMIN (1ULL << 51) -#define RISCV_HWPROBE_EXT_ZVFBFWMA (1ULL << 52) +#define RISCV_HWPROBE_EXT_ZICNTR (1ULL << 50) +#define RISCV_HWPROBE_EXT_ZIHPM (1ULL << 51) ++#define RISCV_HWPROBE_EXT_ZFBFMIN (1ULL << 52) ++#define RISCV_HWPROBE_EXT_ZVFBFMIN (1ULL << 53) ++#define RISCV_HWPROBE_EXT_ZVFBFWMA (1ULL << 54) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)