From: Krzysztof Kozlowski Date: Wed, 13 Mar 2024 18:43:17 +0000 (+0100) Subject: dt-bindings: mtd: Add Samsung S5Pv210 OneNAND X-Git-Tag: microblaze-v6.13~1142^2~8 X-Git-Url: http://git.monstr.eu/?a=commitdiff_plain;h=26729dbb53ac575635ef96ece0442165efa9613f;p=linux-2.6-microblaze.git dt-bindings: mtd: Add Samsung S5Pv210 OneNAND Document binding for Samsung S5Pv210 SoC OneNAND controller used already in S5Pv210 DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20240313184317.18466-1-krzysztof.kozlowski@linaro.org --- diff --git a/Documentation/devicetree/bindings/mtd/samsung,s5pv210-onenand.yaml b/Documentation/devicetree/bindings/mtd/samsung,s5pv210-onenand.yaml new file mode 100644 index 000000000000..e07941b69904 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/samsung,s5pv210-onenand.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/samsung,s5pv210-onenand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S5Pv210 SoC OneNAND Controller + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + enum: + - samsung,s5pv210-onenand + + reg: + items: + - description: Control registers + - description: OneNAND interface nCE[0] + - description: OneNAND interface nCE[1] + + clocks: + maxItems: 2 + + clock-names: + items: + - const: bus + - const: onenand + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +allOf: + - $ref: nand-controller.yaml + +unevaluatedProperties: false + +examples: + - | + #include + + nand-controller@b0600000 { + compatible = "samsung,s5pv210-onenand"; + reg = <0xb0600000 0x2000>, + <0xb0000000 0x20000>, + <0xb0040000 0x20000>; + clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>; + clock-names = "bus", "onenand"; + interrupt-parent = <&vic1>; + interrupts = <31>; + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + }; + };