From: Kan Liang Date: Tue, 8 Oct 2019 15:50:08 +0000 (-0700) Subject: perf/x86/intel: Add Tiger Lake CPU support X-Git-Tag: microblaze-v5.6-rc1~407^2~2 X-Git-Url: http://git.monstr.eu/?a=commitdiff_plain;h=23645a76ba816652d6898def2ee69c6a6250c9b1;p=linux-2.6-microblaze.git perf/x86/intel: Add Tiger Lake CPU support Tiger Lake is the followon to Ice Lake. From the perspective of Intel core PMU, there is little changes compared with Ice Lake, e.g. small changes in event list. But it doesn't impact on core PMU functionality. Share the perf code with Ice Lake. The event list patch will be submitted later separately. The patch has been tested on real hardware. Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Link: https://lkml.kernel.org/r/1570549810-25049-8-git-send-email-kan.liang@linux.intel.com Signed-off-by: Ingo Molnar --- diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 9d91a472e1bb..fcef678c3423 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5033,6 +5033,8 @@ __init int intel_pmu_init(void) /* fall through */ case INTEL_FAM6_ICELAKE_L: case INTEL_FAM6_ICELAKE: + case INTEL_FAM6_TIGERLAKE_L: + case INTEL_FAM6_TIGERLAKE: x86_pmu.late_ack = true; memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids)); memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));