From: Ville Syrjälä Date: Fri, 28 Jan 2022 10:37:57 +0000 (+0200) Subject: drm/i915: Document BDW+ DRRS M/N programming requirements X-Git-Tag: microblaze-v5.19~115^2~23^2~18 X-Git-Url: http://git.monstr.eu/?a=commitdiff_plain;h=19d36cfafad0395d1b8a9db7a85d64282c42ae94;p=linux-2.6-microblaze.git drm/i915: Document BDW+ DRRS M/N programming requirements When reprogramming M/N live on BDW+ we must write the LINK_N register last as it's the one that arms the double buffered register update for all the M/N registers. Document this so that we don't accidentally break things. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20220128103757.22461-18-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index d55f87891c4c..01e8cea0053e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3152,6 +3152,10 @@ void intel_set_m_n(struct drm_i915_private *i915, intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m); intel_de_write(i915, data_n_reg, m_n->data_n); intel_de_write(i915, link_m_reg, m_n->link_m); + /* + * On BDW+ writing LINK_N arms the double buffered update + * of all the M/N registers, so it must be written last. + */ intel_de_write(i915, link_n_reg, m_n->link_n); }