From: Palmer Dabbelt Date: Sat, 5 Oct 2024 15:51:17 +0000 (-0700) Subject: Merge patch series "riscv: Per-thread envcfg CSR support" X-Git-Tag: microblaze-v6.16~520^2~8 X-Git-Url: http://git.monstr.eu/?a=commitdiff_plain;h=1540def11f0c4982de17cc36df1b21eeeb37c355;p=linux-2.6-microblaze.git Merge patch series "riscv: Per-thread envcfg CSR support" Samuel Holland says: This series (or equivalent) is a prerequisite for both user-mode pointer masking and CFI support, as both of those are per-thread features and are controlled by fields in the envcfg CSR. These patches are based on v1 of the pointer masking series[1], with significant input from both Deepak and Andrew. [1]: https://lore.kernel.org/linux-riscv/20240319215915.832127-6-samuel.holland@sifive.com/ * b4-shazam-merge: riscv: Call riscv_user_isa_enable() only on the boot hart riscv: Add support for per-thread envcfg CSR values riscv: Enable cbo.zero only when all harts support Zicboz ink: https://lore.kernel.org/r/20240814081126.956287-1-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt --- 1540def11f0c4982de17cc36df1b21eeeb37c355