ARM: dts: add async-bridge clocks to disp1 power domain for exynos5420

FIMD and MIXER IPs in disp1 power domain have async-bridges (to GSCALER),
therefore their clocks should be enabled during power domain switch.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 9dc2e97..ac0fc09 100644 (file)
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -283,9 +283,11 @@
                         <&clock CLK_MOUT_SW_ACLK300>,
                         <&clock CLK_MOUT_USER_ACLK300_DISP1>,
                         <&clock CLK_MOUT_SW_ACLK400>,
-                        <&clock CLK_MOUT_USER_ACLK400_DISP1>;
+                        <&clock CLK_MOUT_USER_ACLK400_DISP1>,
+                        <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
                clock-names = "oscclk", "pclk0", "clk0",
-                             "pclk1", "clk1", "pclk2", "clk2";
+                             "pclk1", "clk1", "pclk2", "clk2",
+                             "asb0", "asb1";
        };
 
        pinctrl_0: pinctrl@13400000 {