Merge tag 'ti-k3-dt-fixes-for-v5.9' into ti-k3-dts-next

Merge fix up for TI serdes mux definition introduced in 5.9 as
dependency for 5.10 series on J7200 USB.

Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 917421e..52e1211 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -311,11 +311,12 @@
 };
 
 &serdes_ln_ctrl {
-       idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
-                     <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
-                     <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
-                     <SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>,
-                     <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
+       idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
+                     <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
+                     <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
+                     <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
+                     <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
+                     <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
 };
 
 &serdes_wiz3 {

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 824ccd7..e2a96b2 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -6,7 +6,7 @@
  */
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/mux/mux.h>
-#include <dt-bindings/mux/mux-j721e-wiz.h>
+#include <dt-bindings/mux/ti-serdes.h>
 
 &cbass_main {
        msmc_ram: sram@70000000 {
@@ -70,11 +70,12 @@
                                        <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
                                        <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
                                        /* SERDES4 lane0/1/2/3 select */
-                       idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
-                                     <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
-                                     <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
-                                     <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
-                                     <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
+                       idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
+                                     <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
+                                     <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
+                                     <MUX_IDLE_AS_IS>, <J721E_SERDES3_LANE1_USB3_0>,
+                                     <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
+                                     <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
                };
 
                usb_serdes_mux: mux-controller@4000 {

diff --git a/include/dt-bindings/mux/mux-j721e-wiz.h b/include/dt-bindings/mux/mux-j721e-wiz.h
deleted file mode 100644 (file)
index fd1c4ea..0000000
--- a/include/dt-bindings/mux/mux-j721e-wiz.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This header provides constants for J721E WIZ.
- */
-
-#ifndef _DT_BINDINGS_J721E_WIZ
-#define _DT_BINDINGS_J721E_WIZ
-
-#define SERDES0_LANE0_QSGMII_LANE1     0x0
-#define SERDES0_LANE0_PCIE0_LANE0      0x1
-#define SERDES0_LANE0_USB3_0_SWAP      0x2
-
-#define SERDES0_LANE1_QSGMII_LANE2     0x0
-#define SERDES0_LANE1_PCIE0_LANE1      0x1
-#define SERDES0_LANE1_USB3_0           0x2
-
-#define SERDES1_LANE0_QSGMII_LANE3     0x0
-#define SERDES1_LANE0_PCIE1_LANE0      0x1
-#define SERDES1_LANE0_USB3_1_SWAP      0x2
-#define SERDES1_LANE0_SGMII_LANE0      0x3
-
-#define SERDES1_LANE1_QSGMII_LANE4     0x0
-#define SERDES1_LANE1_PCIE1_LANE1      0x1
-#define SERDES1_LANE1_USB3_1           0x2
-#define SERDES1_LANE1_SGMII_LANE1      0x3
-
-#define SERDES2_LANE0_PCIE2_LANE0      0x1
-#define SERDES2_LANE0_SGMII_LANE0      0x3
-#define SERDES2_LANE0_USB3_1_SWAP      0x2
-
-#define SERDES2_LANE1_PCIE2_LANE1      0x1
-#define SERDES2_LANE1_USB3_1           0x2
-#define SERDES2_LANE1_SGMII_LANE1      0x3
-
-#define SERDES3_LANE0_PCIE3_LANE0      0x1
-#define SERDES3_LANE0_USB3_0_SWAP      0x2
-
-#define SERDES3_LANE1_PCIE3_LANE1      0x1
-#define SERDES3_LANE1_USB3_0           0x2
-
-#define SERDES4_LANE0_EDP_LANE0                0x0
-#define SERDES4_LANE0_QSGMII_LANE5     0x2
-
-#define SERDES4_LANE1_EDP_LANE1                0x0
-#define SERDES4_LANE1_QSGMII_LANE6     0x2
-
-#define SERDES4_LANE2_EDP_LANE2                0x0
-#define SERDES4_LANE2_QSGMII_LANE7     0x2
-
-#define SERDES4_LANE3_EDP_LANE3                0x0
-#define SERDES4_LANE3_QSGMII_LANE8     0x2
-
-#endif /* _DT_BINDINGS_J721E_WIZ */

diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h
new file mode 100644 (file)
index 0000000..146d068
--- /dev/null
+++ b/include/dt-bindings/mux/ti-serdes.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for SERDES MUX for TI SoCs
+ */
+
+#ifndef _DT_BINDINGS_MUX_TI_SERDES
+#define _DT_BINDINGS_MUX_TI_SERDES
+
+/* J721E */
+
+#define J721E_SERDES0_LANE0_QSGMII_LANE1       0x0
+#define J721E_SERDES0_LANE0_PCIE0_LANE0                0x1
+#define J721E_SERDES0_LANE0_USB3_0_SWAP                0x2
+#define J721E_SERDES0_LANE0_IP4_UNUSED         0x3
+
+#define J721E_SERDES0_LANE1_QSGMII_LANE2       0x0
+#define J721E_SERDES0_LANE1_PCIE0_LANE1                0x1
+#define J721E_SERDES0_LANE1_USB3_0             0x2
+#define J721E_SERDES0_LANE1_IP4_UNUSED         0x3
+
+#define J721E_SERDES1_LANE0_QSGMII_LANE3       0x0
+#define J721E_SERDES1_LANE0_PCIE1_LANE0                0x1
+#define J721E_SERDES1_LANE0_USB3_1_SWAP                0x2
+#define J721E_SERDES1_LANE0_SGMII_LANE0                0x3
+
+#define J721E_SERDES1_LANE1_QSGMII_LANE4       0x0
+#define J721E_SERDES1_LANE1_PCIE1_LANE1                0x1
+#define J721E_SERDES1_LANE1_USB3_1             0x2
+#define J721E_SERDES1_LANE1_SGMII_LANE1                0x3
+
+#define J721E_SERDES2_LANE0_IP1_UNUSED         0x0
+#define J721E_SERDES2_LANE0_PCIE2_LANE0                0x1
+#define J721E_SERDES2_LANE0_USB3_1_SWAP                0x2
+#define J721E_SERDES2_LANE0_SGMII_LANE0                0x3
+
+#define J721E_SERDES2_LANE1_IP1_UNUSED         0x0
+#define J721E_SERDES2_LANE1_PCIE2_LANE1                0x1
+#define J721E_SERDES2_LANE1_USB3_1             0x2
+#define J721E_SERDES2_LANE1_SGMII_LANE1                0x3
+
+#define J721E_SERDES3_LANE0_IP1_UNUSED         0x0
+#define J721E_SERDES3_LANE0_PCIE3_LANE0                0x1
+#define J721E_SERDES3_LANE0_USB3_0_SWAP                0x2
+#define J721E_SERDES3_LANE0_IP4_UNUSED         0x3
+
+#define J721E_SERDES3_LANE1_IP1_UNUSED         0x0
+#define J721E_SERDES3_LANE1_PCIE3_LANE1                0x1
+#define J721E_SERDES3_LANE1_USB3_0             0x2
+#define J721E_SERDES3_LANE1_IP4_UNUSED         0x3
+
+#define J721E_SERDES4_LANE0_EDP_LANE0          0x0
+#define J721E_SERDES4_LANE0_IP2_UNUSED         0x1
+#define J721E_SERDES4_LANE0_QSGMII_LANE5       0x2
+#define J721E_SERDES4_LANE0_IP4_UNUSED         0x3
+
+#define J721E_SERDES4_LANE1_EDP_LANE1          0x0
+#define J721E_SERDES4_LANE1_IP2_UNUSED         0x1
+#define J721E_SERDES4_LANE1_QSGMII_LANE6       0x2
+#define J721E_SERDES4_LANE1_IP4_UNUSED         0x3
+
+#define J721E_SERDES4_LANE2_EDP_LANE2          0x0
+#define J721E_SERDES4_LANE2_IP2_UNUSED         0x1
+#define J721E_SERDES4_LANE2_QSGMII_LANE7       0x2
+#define J721E_SERDES4_LANE2_IP4_UNUSED         0x3
+
+#define J721E_SERDES4_LANE3_EDP_LANE3          0x0
+#define J721E_SERDES4_LANE3_IP2_UNUSED         0x1
+#define J721E_SERDES4_LANE3_QSGMII_LANE8       0x2
+#define J721E_SERDES4_LANE3_IP4_UNUSED         0x3
+
+#endif /* _DT_BINDINGS_MUX_TI_SERDES */