drm/amdgpu: add helper to enable an ih ring for vega10

vega10_ih_enable_ring will be used to enable an
ih ring for vega10/12, RAVEN series and RENOIR.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index a11553a..42e7897 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -255,6 +255,58 @@ static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
        return ih_doorbell_rtpr;
 }
 
+/**
+ * vega10_ih_enable_ring - enable an ih ring buffer
+ *
+ * @adev: amdgpu_device pointer
+ * @ih: amdgpu_ih_ring pointer
+ *
+ * Enable an ih ring buffer (VEGA10)
+ */
+static int vega10_ih_enable_ring(struct amdgpu_device *adev,
+                                struct amdgpu_ih_ring *ih)
+{
+       struct amdgpu_ih_regs *ih_regs;
+       uint32_t tmp;
+
+       ih_regs = &ih->ih_regs;
+
+       /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
+       WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
+       WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
+
+       tmp = RREG32(ih_regs->ih_rb_cntl);
+       tmp = vega10_ih_rb_cntl(ih, tmp);
+       if (ih == &adev->irq.ih)
+               tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
+       if (ih == &adev->irq.ih1) {
+               tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
+               tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
+       }
+       if (amdgpu_sriov_vf(adev)) {
+               if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
+                       dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
+                       return -ETIMEDOUT;
+               }
+       } else {
+               WREG32(ih_regs->ih_rb_cntl, tmp);
+       }
+
+       if (ih == &adev->irq.ih) {
+               /* set the ih ring 0 writeback address whether it's enabled or not */
+               WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
+               WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
+       }
+
+       /* set rptr, wptr to 0 */
+       WREG32(ih_regs->ih_rb_wptr, 0);
+       WREG32(ih_regs->ih_rb_rptr, 0);
+
+       WREG32(ih_regs->ih_doorbell_rptr, vega10_ih_doorbell_rptr(ih));
+
+       return 0;
+}
+
 /**
  * vega10_ih_irq_init - init and enable the interrupt ring
  *