KVM: TDX: Add accessors VMX VMCS helpers

TDX defines SEAMCALL APIs to access TDX control structures corresponding to
the VMX VMCS.  Introduce helper accessors to hide its SEAMCALL ABI details.

Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
Co-developed-by: Rick Edgecombe <rick.p.edgecombe@intel.com>
Signed-off-by: Rick Edgecombe <rick.p.edgecombe@intel.com>
Co-developed-by: Yan Zhao <yan.y.zhao@intel.com>
Signed-off-by: Yan Zhao <yan.y.zhao@intel.com>
Message-ID: <20241112073551.22070-1-yan.y.zhao@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c
index 01166cb..6932b38 100644 (file)
--- a/arch/x86/kvm/vmx/tdx.c
+++ b/arch/x86/kvm/vmx/tdx.c
@@ -36,6 +36,19 @@ static enum cpuhp_state tdx_cpuhp_state;
 
 static const struct tdx_sys_info *tdx_sysinfo;
 
+void tdh_vp_rd_failed(struct vcpu_tdx *tdx, char *uclass, u32 field, u64 err)
+{
+       KVM_BUG_ON(1, tdx->vcpu.kvm);
+       pr_err("TDH_VP_RD[%s.0x%x] failed 0x%llx\n", uclass, field, err);
+}
+
+void tdh_vp_wr_failed(struct vcpu_tdx *tdx, char *uclass, char *op, u32 field,
+                     u64 val, u64 err)
+{
+       KVM_BUG_ON(1, tdx->vcpu.kvm);
+       pr_err("TDH_VP_WR[%s.0x%x]%s0x%llx failed: 0x%llx\n", uclass, field, op, val, err);
+}
+
 #define KVM_SUPPORTED_TD_ATTRS (TDX_TD_ATTR_SEPT_VE_DISABLE)
 
 static __always_inline struct kvm_tdx *to_kvm_tdx(struct kvm *kvm)

diff --git a/arch/x86/kvm/vmx/tdx.h b/arch/x86/kvm/vmx/tdx.h
index 0559126..b3029e6 100644 (file)
--- a/arch/x86/kvm/vmx/tdx.h
+++ b/arch/x86/kvm/vmx/tdx.h
@@ -48,6 +48,10 @@ struct vcpu_tdx {
        enum vcpu_tdx_state state;
 };
 
+void tdh_vp_rd_failed(struct vcpu_tdx *tdx, char *uclass, u32 field, u64 err);
+void tdh_vp_wr_failed(struct vcpu_tdx *tdx, char *uclass, char *op, u32 field,
+                     u64 val, u64 err);
+
 static inline bool is_td(struct kvm *kvm)
 {
        return kvm->arch.vm_type == KVM_X86_TDX_VM;
@@ -69,6 +73,90 @@ static __always_inline u64 td_tdcs_exec_read64(struct kvm_tdx *kvm_tdx, u32 fiel
        }
        return data;
 }
+
+static __always_inline void tdvps_vmcs_check(u32 field, u8 bits)
+{
+#define VMCS_ENC_ACCESS_TYPE_MASK      0x1UL
+#define VMCS_ENC_ACCESS_TYPE_FULL      0x0UL
+#define VMCS_ENC_ACCESS_TYPE_HIGH      0x1UL
+#define VMCS_ENC_ACCESS_TYPE(field)    ((field) & VMCS_ENC_ACCESS_TYPE_MASK)
+
+       /* TDX is 64bit only.  HIGH field isn't supported. */
+       BUILD_BUG_ON_MSG(__builtin_constant_p(field) &&
+                        VMCS_ENC_ACCESS_TYPE(field) == VMCS_ENC_ACCESS_TYPE_HIGH,
+                        "Read/Write to TD VMCS *_HIGH fields not supported");
+
+       BUILD_BUG_ON(bits != 16 && bits != 32 && bits != 64);
+
+#define VMCS_ENC_WIDTH_MASK    GENMASK(14, 13)
+#define VMCS_ENC_WIDTH_16BIT   (0UL << 13)
+#define VMCS_ENC_WIDTH_64BIT   (1UL << 13)
+#define VMCS_ENC_WIDTH_32BIT   (2UL << 13)
+#define VMCS_ENC_WIDTH_NATURAL (3UL << 13)
+#define VMCS_ENC_WIDTH(field)  ((field) & VMCS_ENC_WIDTH_MASK)
+
+       /* TDX is 64bit only.  i.e. natural width = 64bit. */
+       BUILD_BUG_ON_MSG(bits != 64 && __builtin_constant_p(field) &&
+                        (VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_64BIT ||
+                         VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_NATURAL),
+                        "Invalid TD VMCS access for 64-bit field");
+       BUILD_BUG_ON_MSG(bits != 32 && __builtin_constant_p(field) &&
+                        VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_32BIT,
+                        "Invalid TD VMCS access for 32-bit field");
+       BUILD_BUG_ON_MSG(bits != 16 && __builtin_constant_p(field) &&
+                        VMCS_ENC_WIDTH(field) == VMCS_ENC_WIDTH_16BIT,
+                        "Invalid TD VMCS access for 16-bit field");
+}
+
+#define TDX_BUILD_TDVPS_ACCESSORS(bits, uclass, lclass)                                \
+static __always_inline u##bits td_##lclass##_read##bits(struct vcpu_tdx *tdx,  \
+                                                       u32 field)              \
+{                                                                              \
+       u64 err, data;                                                          \
+                                                                               \
+       tdvps_##lclass##_check(field, bits);                                    \
+       err = tdh_vp_rd(&tdx->vp, TDVPS_##uclass(field), &data);                \
+       if (unlikely(err)) {                                                    \
+               tdh_vp_rd_failed(tdx, #uclass, field, err);                     \
+               return 0;                                                       \
+       }                                                                       \
+       return (u##bits)data;                                                   \
+}                                                                              \
+static __always_inline void td_##lclass##_write##bits(struct vcpu_tdx *tdx,    \
+                                                     u32 field, u##bits val)   \
+{                                                                              \
+       u64 err;                                                                \
+                                                                               \
+       tdvps_##lclass##_check(field, bits);                                    \
+       err = tdh_vp_wr(&tdx->vp, TDVPS_##uclass(field), val,                   \
+                     GENMASK_ULL(bits - 1, 0));                                \
+       if (unlikely(err))                                                      \
+               tdh_vp_wr_failed(tdx, #uclass, " = ", field, (u64)val, err);    \
+}                                                                              \
+static __always_inline void td_##lclass##_setbit##bits(struct vcpu_tdx *tdx,   \
+                                                      u32 field, u64 bit)      \
+{                                                                              \
+       u64 err;                                                                \
+                                                                               \
+       tdvps_##lclass##_check(field, bits);                                    \
+       err = tdh_vp_wr(&tdx->vp, TDVPS_##uclass(field), bit, bit);             \
+       if (unlikely(err))                                                      \
+               tdh_vp_wr_failed(tdx, #uclass, " |= ", field, bit, err);        \
+}                                                                              \
+static __always_inline void td_##lclass##_clearbit##bits(struct vcpu_tdx *tdx, \
+                                                        u32 field, u64 bit)    \
+{                                                                              \
+       u64 err;                                                                \
+                                                                               \
+       tdvps_##lclass##_check(field, bits);                                    \
+       err = tdh_vp_wr(&tdx->vp, TDVPS_##uclass(field), 0, bit);               \
+       if (unlikely(err))                                                      \
+               tdh_vp_wr_failed(tdx, #uclass, " &= ~", field, bit, err);\
+}
+
+TDX_BUILD_TDVPS_ACCESSORS(16, VMCS, vmcs);
+TDX_BUILD_TDVPS_ACCESSORS(32, VMCS, vmcs);
+TDX_BUILD_TDVPS_ACCESSORS(64, VMCS, vmcs);
 #else
 static inline int tdx_bringup(void) { return 0; }
 static inline void tdx_cleanup(void) {}