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drm/xe/i2c: Enable bus mastering
author
Raag Jadav
<raag.jadav@intel.com>
Mon, 8 Sep 2025 05:53:20 +0000
(11:23 +0530)
committer
Lucas De Marchi
<lucas.demarchi@intel.com>
Tue, 9 Sep 2025 13:02:35 +0000
(06:02 -0700)
Enable bus mastering for I2C controller to support device initiated
in-band transactions.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Link:
https://lore.kernel.org/r/20250908055320.2549722-1-raag.jadav@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
drivers/gpu/drm/xe/xe_i2c.c
patch
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diff --git
a/drivers/gpu/drm/xe/xe_i2c.c
b/drivers/gpu/drm/xe/xe_i2c.c
index
044dda5
..
48dfcb4
100644
(file)
--- a/
drivers/gpu/drm/xe/xe_i2c.c
+++ b/
drivers/gpu/drm/xe/xe_i2c.c
@@
-259,7
+259,7
@@
void xe_i2c_pm_resume(struct xe_device *xe, bool d3cold)
return;
if (d3cold)
- xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, 0, PCI_COMMAND_MEMORY);
+ xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, 0, PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
xe_mmio_rmw32(mmio, I2C_CONFIG_PMCSR, PCI_PM_CTRL_STATE_MASK, (__force u32)PCI_D0);
drm_dbg(&xe->drm, "pmcsr: 0x%08x\n", xe_mmio_read32(mmio, I2C_CONFIG_PMCSR));