arm64: dts: qcom: sm8350: Update the RPMHPD bindings entry
authorRohit Agarwal <quic_rohiagar@quicinc.com>
Thu, 20 Jul 2023 08:09:03 +0000 (13:39 +0530)
committerBjorn Andersson <andersson@kernel.org>
Sat, 22 Jul 2023 02:59:44 +0000 (19:59 -0700)
Update the RPMHPD bindings entry as per the new generic bindings defined in
rpmhpd.h for SM8350 SoC.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Link: https://lore.kernel.org/r/1689840545-5094-3-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arch/arm64/boot/dts/qcom/sm8350.dtsi

index b1f9f44..d34d02a 100644 (file)
@@ -15,6 +15,7 @@
 #include <dt-bindings/mailbox/qcom-ipcc.h>
 #include <dt-bindings/phy/phy-qcom-qmp.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/power/qcom,rpmhpd.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 #include <dt-bindings/thermal/thermal.h>
 #include <dt-bindings/interconnect/qcom,sm8350.h>
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
                                interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_120mhz>;
                                dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
                                       <&gpi_dma2 1 0 QCOM_GPI_SPI>;
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
                                interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_120mhz>;
                                dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
                                       <&gpi_dma2 1 1 QCOM_GPI_SPI>;
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
                                interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
                                       <&gpi_dma2 1 2 QCOM_GPI_SPI>;
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
                                interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
                                       <&gpi_dma2 1 3 QCOM_GPI_SPI>;
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
                                interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
                                       <&gpi_dma2 1 4 QCOM_GPI_SPI>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&qup_uart18_default>;
                                interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                status = "disabled";
                        };
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
                                interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
                                       <&gpi_dma2 1 5 QCOM_GPI_SPI>;
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
                                interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
                                       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
                                interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
                                       <&gpi_dma0 1 1 QCOM_GPI_SPI>;
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
                                interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
                                       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&qup_uart3_default_state>;
                                interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                status = "disabled";
                        };
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
                                interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
                                       <&gpi_dma0 1 3 QCOM_GPI_SPI>;
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
                                interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
                                       <&gpi_dma0 1 4 QCOM_GPI_SPI>;
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
                                interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
                                       <&gpi_dma0 1 5 QCOM_GPI_SPI>;
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
                                interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
                                       <&gpi_dma0 1 6 QCOM_GPI_SPI>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&qup_uart6_default>;
                                interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                status = "disabled";
                        };
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
                                interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
                                       <&gpi_dma0 1 7 QCOM_GPI_SPI>;
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
                                interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_120mhz>;
                                dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
                                       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
                                interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
                                       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
                                interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
                                       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
                                interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
                                       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
                                interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
                                       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
                                clock-names = "se";
                                clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
                                interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
-                               power-domains = <&rpmhpd SM8350_CX>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
                                operating-points-v2 = <&qup_opp_table_100mhz>;
                                dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
                                       <&gpi_dma1 1 5 QCOM_GPI_SPI>;
                        clocks = <&rpmhcc RPMH_CXO_CLK>;
                        clock-names = "xo";
 
-                       power-domains = <&rpmhpd SM8350_CX>,
-                                       <&rpmhpd SM8350_MSS>;
+                       power-domains = <&rpmhpd RPMHPD_CX>,
+                                       <&rpmhpd RPMHPD_MSS>;
                        power-domain-names = "cx", "mss";
 
                        interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
                        clocks = <&rpmhcc RPMH_CXO_CLK>;
                        clock-names = "xo";
 
-                       power-domains = <&rpmhpd SM8350_LCX>,
-                                       <&rpmhpd SM8350_LMX>;
+                       power-domains = <&rpmhpd RPMHPD_LCX>,
+                                       <&rpmhpd RPMHPD_LMX>;
                        power-domain-names = "lcx", "lmx";
 
                        memory-region = <&pil_slpi_mem>;
                                        <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
                        interconnect-names = "sdhc-ddr","cpu-sdhc";
                        iommus = <&apps_smmu 0x4a0 0x0>;
-                       power-domains = <&rpmhpd SM8350_CX>;
+                       power-domains = <&rpmhpd RPMHPD_CX>;
                        operating-points-v2 = <&sdhc2_opp_table>;
                        bus-width = <4>;
                        dma-coherent;
                                assigned-clock-rates = <19200000>;
 
                                operating-points-v2 = <&dpu_opp_table>;
-                               power-domains = <&rpmhpd SM8350_MMCX>;
+                               power-domains = <&rpmhpd RPMHPD_MMCX>;
 
                                interrupt-parent = <&mdss>;
                                interrupts = <0>;
                                #sound-dai-cells = <0>;
 
                                operating-points-v2 = <&dp_opp_table>;
-                               power-domains = <&rpmhpd SM8350_MMCX>;
+                               power-domains = <&rpmhpd RPMHPD_MMCX>;
 
                                status = "disabled";
 
                                                         <&mdss_dsi0_phy 1>;
 
                                operating-points-v2 = <&dsi0_opp_table>;
-                               power-domains = <&rpmhpd SM8350_MMCX>;
+                               power-domains = <&rpmhpd RPMHPD_MMCX>;
 
                                phys = <&mdss_dsi0_phy>;
 
                                                         <&mdss_dsi1_phy 1>;
 
                                operating-points-v2 = <&dsi1_opp_table>;
-                               power-domains = <&rpmhpd SM8350_MMCX>;
+                               power-domains = <&rpmhpd RPMHPD_MMCX>;
 
                                phys = <&mdss_dsi1_phy>;
 
                        #reset-cells = <1>;
                        #power-domain-cells = <1>;
 
-                       power-domains = <&rpmhpd SM8350_MMCX>;
+                       power-domains = <&rpmhpd RPMHPD_MMCX>;
                };
 
                pdc: interrupt-controller@b220000 {
                        clocks = <&rpmhcc RPMH_CXO_CLK>;
                        clock-names = "xo";
 
-                       power-domains = <&rpmhpd SM8350_LCX>,
-                                       <&rpmhpd SM8350_LMX>;
+                       power-domains = <&rpmhpd RPMHPD_LCX>,
+                                       <&rpmhpd RPMHPD_LMX>;
                        power-domain-names = "lcx", "lmx";
 
                        memory-region = <&pil_adsp_mem>;
                        clocks = <&rpmhcc RPMH_CXO_CLK>;
                        clock-names = "xo";
 
-                       power-domains = <&rpmhpd SM8350_CX>,
-                                       <&rpmhpd SM8350_MXC>;
+                       power-domains = <&rpmhpd RPMHPD_CX>,
+                                       <&rpmhpd RPMHPD_MXC>;
                        power-domain-names = "cx", "mxc";
 
                        interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;