drm/amd/swsmu: add smu 14.0.1 vcn and jpeg msg

add new vcn and jpeg msg

v2: squash in updates (Alex)
v3: rework code for better compat with other smu14.x variants (Alex)

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: lima1002 <li.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_ppsmc.h
index 8a8a57c..ca7ce42 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_ppsmc.h
@@ -54,14 +54,14 @@
 #define PPSMC_MSG_TestMessage                   0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
 #define PPSMC_MSG_GetPmfwVersion                0x02 ///< Get PMFW version
 #define PPSMC_MSG_GetDriverIfVersion            0x03 ///< Get PMFW_DRIVER_IF version
-#define PPSMC_MSG_SPARE0                        0x04 ///< SPARE
-#define PPSMC_MSG_SPARE1                        0x05 ///< SPARE
-#define PPSMC_MSG_PowerDownVcn                  0x06 ///< Power down VCN
-#define PPSMC_MSG_PowerUpVcn                    0x07 ///< Power up VCN; VCN is power gated by default
-#define PPSMC_MSG_SetHardMinVcn                 0x08 ///< For wireless display
+#define PPSMC_MSG_PowerDownVcn1                 0x04 ///< Power down VCN1
+#define PPSMC_MSG_PowerUpVcn1                   0x05 ///< Power up VCN1; VCN1 is power gated by default
+#define PPSMC_MSG_PowerDownVcn0                 0x06 ///< Power down VCN0
+#define PPSMC_MSG_PowerUpVcn0                   0x07 ///< Power up VCN0; VCN0 is power gated by default
+#define PPSMC_MSG_SetHardMinVcn0                0x08 ///< For wireless display
 #define PPSMC_MSG_SetSoftMinGfxclk              0x09 ///< Set SoftMin for GFXCLK, argument is frequency in MHz
-#define PPSMC_MSG_SPARE2                        0x0A ///< SPARE
-#define PPSMC_MSG_SPARE3                        0x0B ///< SPARE
+#define PPSMC_MSG_SetHardMinVcn1                0x0A ///< For wireless display
+#define PPSMC_MSG_SetSoftMinVcn1                0x0B ///< Set soft min for VCN1 clocks (VCLK1 and DCLK1)
 #define PPSMC_MSG_PrepareMp1ForUnload           0x0C ///< Prepare PMFW for GFX driver unload
 #define PPSMC_MSG_SetDriverDramAddrHigh         0x0D ///< Set high 32 bits of DRAM address for Driver table transfer
 #define PPSMC_MSG_SetDriverDramAddrLow          0x0E ///< Set low 32 bits of DRAM address for Driver table transfer
@@ -71,7 +71,7 @@
 #define PPSMC_MSG_GetEnabledSmuFeatures         0x12 ///< Get enabled features in PMFW
 #define PPSMC_MSG_SetHardMinSocclkByFreq        0x13 ///< Set hard min for SOC CLK
 #define PPSMC_MSG_SetSoftMinFclk                0x14 ///< Set hard min for FCLK
-#define PPSMC_MSG_SetSoftMinVcn                 0x15 ///< Set soft min for VCN clocks (VCLK and DCLK)
+#define PPSMC_MSG_SetSoftMinVcn0                0x15 ///< Set soft min for VCN0 clocks (VCLK0 and DCLK0)
 
 #define PPSMC_MSG_EnableGfxImu                  0x16 ///< Enable GFX IMU
 
@@ -84,17 +84,17 @@
 
 #define PPSMC_MSG_SetSoftMaxSocclkByFreq        0x1D ///< Set soft max for SOC CLK
 #define PPSMC_MSG_SetSoftMaxFclkByFreq          0x1E ///< Set soft max for FCLK
-#define PPSMC_MSG_SetSoftMaxVcn                 0x1F ///< Set soft max for VCN clocks (VCLK and DCLK)
+#define PPSMC_MSG_SetSoftMaxVcn0                0x1F ///< Set soft max for VCN0 clocks (VCLK0 and DCLK0)
 #define PPSMC_MSG_spare_0x20                    0x20
-#define PPSMC_MSG_PowerDownJpeg                 0x21 ///< Power down Jpeg
-#define PPSMC_MSG_PowerUpJpeg                   0x22 ///< Power up Jpeg; VCN is power gated by default
+#define PPSMC_MSG_PowerDownJpeg0                0x21 ///< Power down Jpeg of VCN0
+#define PPSMC_MSG_PowerUpJpeg0                  0x22 ///< Power up Jpeg of VCN0; VCN0 is power gated by default
 
 #define PPSMC_MSG_SetHardMinFclkByFreq          0x23 ///< Set hard min for FCLK
 #define PPSMC_MSG_SetSoftMinSocclkByFreq        0x24 ///< Set soft min for SOC CLK
 #define PPSMC_MSG_AllowZstates                  0x25 ///< Inform PMFM of allowing Zstate entry, i.e. no Miracast activity
-#define PPSMC_MSG_Reserved                      0x26 ///< Not used
-#define PPSMC_MSG_Reserved1                     0x27 ///< Not used, previously PPSMC_MSG_RequestActiveWgp
-#define PPSMC_MSG_Reserved2                     0x28 ///< Not used, previously PPSMC_MSG_QueryActiveWgp
+#define PPSMC_MSG_PowerDownJpeg1                0x26 ///< Power down Jpeg of VCN1
+#define PPSMC_MSG_PowerUpJpeg1                  0x27 ///< Power up Jpeg of VCN1; VCN1 is power gated by default
+#define PPSMC_MSG_SetSoftMaxVcn1                0x28 ///< Set soft max for VCN1 clocks (VCLK1 and DCLK1)
 #define PPSMC_MSG_PowerDownIspByTile            0x29 ///< ISP is power gated by default
 #define PPSMC_MSG_PowerUpIspByTile              0x2A ///< This message is used to power up ISP tiles and enable the ISP DPM
 #define PPSMC_MSG_SetHardMinIspiclkByFreq       0x2B ///< Set HardMin by frequency for ISPICLK

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
index a941fdb..af427cc 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
@@ -115,6 +115,10 @@
        __SMU_DUMMY_MAP(PowerDownVcn),                 \
        __SMU_DUMMY_MAP(PowerUpJpeg),                  \
        __SMU_DUMMY_MAP(PowerDownJpeg),                \
+       __SMU_DUMMY_MAP(PowerUpJpeg0),                 \
+       __SMU_DUMMY_MAP(PowerDownJpeg0),               \
+       __SMU_DUMMY_MAP(PowerUpJpeg1),                 \
+       __SMU_DUMMY_MAP(PowerDownJpeg1),               \
        __SMU_DUMMY_MAP(BacoAudioD3PME),               \
        __SMU_DUMMY_MAP(ArmD3),                        \
        __SMU_DUMMY_MAP(RunDcBtc),                     \
@@ -135,6 +139,8 @@
        __SMU_DUMMY_MAP(PowerUpSdma),                 \
        __SMU_DUMMY_MAP(SetHardMinIspclkByFreq),      \
        __SMU_DUMMY_MAP(SetHardMinVcn),               \
+       __SMU_DUMMY_MAP(SetHardMinVcn0),               \
+       __SMU_DUMMY_MAP(SetHardMinVcn1),               \
        __SMU_DUMMY_MAP(SetAllowFclkSwitch),          \
        __SMU_DUMMY_MAP(SetMinVideoGfxclkFreq),       \
        __SMU_DUMMY_MAP(ActiveProcessNotify),         \
@@ -150,6 +156,8 @@
        __SMU_DUMMY_MAP(SetPhyclkVoltageByFreq),      \
        __SMU_DUMMY_MAP(SetDppclkVoltageByFreq),      \
        __SMU_DUMMY_MAP(SetSoftMinVcn),               \
+       __SMU_DUMMY_MAP(SetSoftMinVcn0),              \
+       __SMU_DUMMY_MAP(SetSoftMinVcn1),              \
        __SMU_DUMMY_MAP(EnablePostCode),              \
        __SMU_DUMMY_MAP(GetGfxclkFrequency),          \
        __SMU_DUMMY_MAP(GetFclkFrequency),            \
@@ -161,6 +169,8 @@
        __SMU_DUMMY_MAP(SetSoftMaxSocclkByFreq),      \
        __SMU_DUMMY_MAP(SetSoftMaxFclkByFreq),        \
        __SMU_DUMMY_MAP(SetSoftMaxVcn),               \
+       __SMU_DUMMY_MAP(SetSoftMaxVcn0),              \
+       __SMU_DUMMY_MAP(SetSoftMaxVcn1),              \
        __SMU_DUMMY_MAP(PowerGateMmHub),              \
        __SMU_DUMMY_MAP(UpdatePmeRestore),            \
        __SMU_DUMMY_MAP(GpuChangeState),              \

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
index b06a3cc..9e39f99 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
@@ -1402,9 +1402,22 @@ int smu_v14_0_set_vcn_enable(struct smu_context *smu,
                if (adev->vcn.harvest_config & (1 << i))
                        continue;
 
-               ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
-                                                     SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
-                                                     i << 16U, NULL);
+               if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||
+                   amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {
+                       if (i == 0)
+                               ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
+                                                                     SMU_MSG_PowerUpVcn0 : SMU_MSG_PowerDownVcn0,
+                                                                     i << 16U, NULL);
+                       else if (i == 1)
+                               ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
+                                                                     SMU_MSG_PowerUpVcn1 : SMU_MSG_PowerDownVcn1,
+                                                                     i << 16U, NULL);
+               } else {
+                       ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
+                                                             SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
+                                                             i << 16U, NULL);
+               }
+
                if (ret)
                        return ret;
        }
@@ -1415,9 +1428,34 @@ int smu_v14_0_set_vcn_enable(struct smu_context *smu,
 int smu_v14_0_set_jpeg_enable(struct smu_context *smu,
                              bool enable)
 {
-       return smu_cmn_send_smc_msg_with_param(smu, enable ?
-                                              SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
-                                              0, NULL);
+       struct amdgpu_device *adev = smu->adev;
+       int i, ret = 0;
+
+       for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
+               if (adev->jpeg.harvest_config & (1 << i))
+                       continue;
+
+               if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||
+                   amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {
+                       if (i == 0)
+                               ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
+                                                                     SMU_MSG_PowerUpJpeg0 : SMU_MSG_PowerDownJpeg0,
+                                                                     i << 16U, NULL);
+                       else if (i == 1 && amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
+                               ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
+                                                                     SMU_MSG_PowerUpJpeg1 : SMU_MSG_PowerDownJpeg1,
+                                                                     i << 16U, NULL);
+               } else {
+                       ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
+                                                             SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
+                                                             i << 16U, NULL);
+               }
+
+               if (ret)
+                       return ret;
+       }
+
+       return ret;
 }
 
 int smu_v14_0_run_btc(struct smu_context *smu)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
index 9310c47..d6de6d9 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
@@ -70,9 +70,12 @@ static struct cmn2asic_msg_mapping smu_v14_0_0_message_map[SMU_MSG_MAX_COUNT] =
        MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                          1),
        MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetPmfwVersion,                       1),
        MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,           1),
-       MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                         1),
-       MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                           1),
-       MSG_MAP(SetHardMinVcn,                  PPSMC_MSG_SetHardMinVcn,                        1),
+       MSG_MAP(PowerDownVcn0,                  PPSMC_MSG_PowerDownVcn0,                        1),
+       MSG_MAP(PowerUpVcn0,                    PPSMC_MSG_PowerUpVcn0,                          1),
+       MSG_MAP(SetHardMinVcn0,                 PPSMC_MSG_SetHardMinVcn0,                       1),
+       MSG_MAP(PowerDownVcn1,                  PPSMC_MSG_PowerDownVcn1,                        1),
+       MSG_MAP(PowerUpVcn1,                    PPSMC_MSG_PowerUpVcn1,                          1),
+       MSG_MAP(SetHardMinVcn1,                 PPSMC_MSG_SetHardMinVcn1,                       1),
        MSG_MAP(SetSoftMinGfxclk,               PPSMC_MSG_SetSoftMinGfxclk,                     1),
        MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,          1),
        MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,        1),
@@ -83,7 +86,8 @@ static struct cmn2asic_msg_mapping smu_v14_0_0_message_map[SMU_MSG_MAX_COUNT] =
        MSG_MAP(GetEnabledSmuFeatures,          PPSMC_MSG_GetEnabledSmuFeatures,        1),
        MSG_MAP(SetHardMinSocclkByFreq,         PPSMC_MSG_SetHardMinSocclkByFreq,       1),
        MSG_MAP(SetSoftMinFclk,                 PPSMC_MSG_SetSoftMinFclk,                       1),
-       MSG_MAP(SetSoftMinVcn,                  PPSMC_MSG_SetSoftMinVcn,                        1),
+       MSG_MAP(SetSoftMinVcn0,                 PPSMC_MSG_SetSoftMinVcn0,                       1),
+       MSG_MAP(SetSoftMinVcn1,                 PPSMC_MSG_SetSoftMinVcn1,                       1),
        MSG_MAP(EnableGfxImu,                   PPSMC_MSG_EnableGfxImu,                         1),
        MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                          1),
        MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,                       1),
@@ -91,9 +95,12 @@ static struct cmn2asic_msg_mapping smu_v14_0_0_message_map[SMU_MSG_MAX_COUNT] =
        MSG_MAP(SetHardMinGfxClk,               PPSMC_MSG_SetHardMinGfxClk,                     1),
        MSG_MAP(SetSoftMaxSocclkByFreq,         PPSMC_MSG_SetSoftMaxSocclkByFreq,       1),
        MSG_MAP(SetSoftMaxFclkByFreq,           PPSMC_MSG_SetSoftMaxFclkByFreq,         1),
-       MSG_MAP(SetSoftMaxVcn,                  PPSMC_MSG_SetSoftMaxVcn,                        1),
-       MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,                        1),
-       MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                          1),
+       MSG_MAP(SetSoftMaxVcn0,                 PPSMC_MSG_SetSoftMaxVcn0,                       1),
+       MSG_MAP(SetSoftMaxVcn1,                 PPSMC_MSG_SetSoftMaxVcn1,                       1),
+       MSG_MAP(PowerDownJpeg0,                 PPSMC_MSG_PowerDownJpeg0,                       1),
+       MSG_MAP(PowerUpJpeg0,                   PPSMC_MSG_PowerUpJpeg0,                         1),
+       MSG_MAP(PowerDownJpeg1,                 PPSMC_MSG_PowerDownJpeg1,                       1),
+       MSG_MAP(PowerUpJpeg1,                   PPSMC_MSG_PowerUpJpeg1,                         1),
        MSG_MAP(SetHardMinFclkByFreq,           PPSMC_MSG_SetHardMinFclkByFreq,         1),
        MSG_MAP(SetSoftMinSocclkByFreq,         PPSMC_MSG_SetSoftMinSocclkByFreq,       1),
        MSG_MAP(PowerDownIspByTile,             PPSMC_MSG_PowerDownIspByTile,           1),