{ .name = "hi6421v600-regulator", },
};
-/*
- * The PMIC register is only 8-bit.
- * Hisilicon SoC use hardware to map PMIC register into SoC mapping.
- * At here, we are accessing SoC register with 32-bit.
- */
-int hi6421_spmi_pmic_read(struct hi6421_spmi_pmic *pmic, int reg)
+static irqreturn_t hi6421_spmi_irq_handler(int irq, void *priv)
{
- struct spmi_device *pdev;
- u8 read_value = 0;
- u32 ret;
-
- pdev = to_spmi_device(pmic->dev);
- if (!pdev) {
- pr_err("%s: pdev get failed!\n", __func__);
- return -ENODEV;
- }
-
- ret = spmi_ext_register_readl(pdev, reg, &read_value, 1);
- if (ret) {
- pr_err("%s: spmi_ext_register_readl failed!\n", __func__);
- return ret;
- }
- return read_value;
-}
-EXPORT_SYMBOL(hi6421_spmi_pmic_read);
-
-int hi6421_spmi_pmic_write(struct hi6421_spmi_pmic *pmic, int reg, u32 val)
-{
- struct spmi_device *pdev;
- u32 ret;
-
- pdev = to_spmi_device(pmic->dev);
- if (!pdev) {
- pr_err("%s: pdev get failed!\n", __func__);
- return -ENODEV;
- }
-
- ret = spmi_ext_register_writel(pdev, reg, (unsigned char *)&val, 1);
- if (ret)
- pr_err("%s: spmi_ext_register_writel failed!\n", __func__);
-
- return ret;
-}
-EXPORT_SYMBOL(hi6421_spmi_pmic_write);
-
-int hi6421_spmi_pmic_rmw(struct hi6421_spmi_pmic *pmic, int reg,
- u32 mask, u32 bits)
-{
- unsigned long flags;
- u32 data;
- int ret;
-
- spin_lock_irqsave(&pmic->lock, flags);
- data = hi6421_spmi_pmic_read(pmic, reg) & ~mask;
- data |= mask & bits;
- ret = hi6421_spmi_pmic_write(pmic, reg, data);
- spin_unlock_irqrestore(&pmic->lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(hi6421_spmi_pmic_rmw);
-
-static irqreturn_t hi6421_spmi_irq_handler(int irq, void *data)
-{
- struct hi6421_spmi_pmic *pmic = (struct hi6421_spmi_pmic *)data;
+ struct hi6421_spmi_pmic *pmic = (struct hi6421_spmi_pmic *)priv;
unsigned long pending;
+ unsigned int data;
int i, offset;
for (i = 0; i < HISI_IRQ_ARRAY; i++) {
- pending = hi6421_spmi_pmic_read(pmic, (i + SOC_PMIC_IRQ0_ADDR));
- pending &= HISI_MASK_FIELD;
- if (pending != 0)
- pr_debug("pending[%d]=0x%lx\n\r", i, pending);
+ regmap_read(pmic->map, offset, &data);
+ data &= HISI_MASK_FIELD;
+ if (data != 0)
+ pr_debug("data[%d]=0x%d\n\r", i, data);
+ regmap_write(pmic->map, i + SOC_PMIC_IRQ0_ADDR, data);
- hi6421_spmi_pmic_write(pmic, (i + SOC_PMIC_IRQ0_ADDR), pending);
+ /* for_each_set_bit() macro requires unsigned long */
+ pending = data;
/* solve powerkey order */
if ((i == HISI_IRQ_KEY_NUM) &&
static void hi6421_spmi_irq_mask(struct irq_data *d)
{
struct hi6421_spmi_pmic *pmic = irq_data_get_irq_chip_data(d);
- u32 data, offset;
unsigned long flags;
+ unsigned int data;
+ u32 offset;
offset = (irqd_to_hwirq(d) >> 3);
offset += SOC_PMIC_IRQ_MASK_0_ADDR;
spin_lock_irqsave(&pmic->lock, flags);
- data = hi6421_spmi_pmic_read(pmic, offset);
+
+ regmap_read(pmic->map, offset, &data);
data |= (1 << (irqd_to_hwirq(d) & 0x07));
- hi6421_spmi_pmic_write(pmic, offset, data);
+ regmap_write(pmic->map, offset, data);
spin_unlock_irqrestore(&pmic->lock, flags);
}
offset += SOC_PMIC_IRQ_MASK_0_ADDR;
spin_lock_irqsave(&pmic->lock, flags);
- data = hi6421_spmi_pmic_read(pmic, offset);
+ regmap_read(pmic->map, offset, &data);
data &= ~(1 << (irqd_to_hwirq(d) & 0x07));
- hi6421_spmi_pmic_write(pmic, offset, data);
+ regmap_write(pmic->map, offset, data);
spin_unlock_irqrestore(&pmic->lock, flags);
}
static void hi6421_spmi_pmic_irq_prc(struct hi6421_spmi_pmic *pmic)
{
- int i, pending;
+ int i;
+ unsigned int pending;
for (i = 0 ; i < HISI_IRQ_ARRAY; i++)
- hi6421_spmi_pmic_write(pmic, SOC_PMIC_IRQ_MASK_0_ADDR + i,
+ regmap_write(pmic->map, SOC_PMIC_IRQ_MASK_0_ADDR + i,
HISI_MASK_STATE);
for (i = 0 ; i < HISI_IRQ_ARRAY; i++) {
- pending = hi6421_spmi_pmic_read(pmic, SOC_PMIC_IRQ0_ADDR + i);
+ regmap_read(pmic->map, SOC_PMIC_IRQ0_ADDR + i, &pending);
pr_debug("PMU IRQ address value:irq[0x%x] = 0x%x\n",
SOC_PMIC_IRQ0_ADDR + i, pending);
- hi6421_spmi_pmic_write(pmic, SOC_PMIC_IRQ0_ADDR + i,
- HISI_MASK_STATE);
+ regmap_write(pmic->map, SOC_PMIC_IRQ0_ADDR + i,
+ HISI_MASK_STATE);
}
}
+static const struct regmap_config spmi_regmap_config = {
+ .reg_bits = 16,
+ .val_bits = 8,
+ .max_register = 0xffff,
+ .fast_io = true
+};
+
static int hi6421_spmi_pmic_probe(struct spmi_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct hi6421_spmi_pmic *pmic;
+ struct regmap *map;
unsigned int virq;
int ret, i;
if (!pmic)
return -ENOMEM;
+ map = devm_regmap_init_spmi_ext(pdev, &spmi_regmap_config);
+ if (IS_ERR(map))
+ return PTR_ERR(map);
+
spin_lock_init(&pmic->lock);
pmic->dev = dev;
+ pmic->map = map;
pmic->gpio = of_get_gpio(np, 0);
if (pmic->gpio < 0)
#include <linux/mfd/hi6421-spmi-pmic.h>
#include <linux/module.h>
#include <linux/platform_device.h>
+#include <linux/regmap.h>
#include <linux/regulator/driver.h>
#include <linux/spmi.h>
struct hi6421_spmi_pmic *pmic = sreg->pmic;
u32 reg_val;
- reg_val = hi6421_spmi_pmic_read(pmic, rdev->desc->enable_reg);
+ regmap_read(pmic->map, rdev->desc->enable_reg, ®_val);
return ((reg_val & rdev->desc->enable_mask) != 0);
}
/* cannot enable more than one regulator at one time */
mutex_lock(&sreg->enable_mutex);
- ret = hi6421_spmi_pmic_rmw(pmic, rdev->desc->enable_reg,
- rdev->desc->enable_mask,
- rdev->desc->enable_mask);
+ ret = regmap_update_bits(pmic->map, rdev->desc->enable_reg,
+ rdev->desc->enable_mask,
+ rdev->desc->enable_mask);
/* Avoid powering up multiple devices at the same time */
usleep_range(rdev->desc->off_on_delay, rdev->desc->off_on_delay + 60);
struct hi6421_spmi_reg_info *sreg = rdev_get_drvdata(rdev);
struct hi6421_spmi_pmic *pmic = sreg->pmic;
- return hi6421_spmi_pmic_rmw(pmic, rdev->desc->enable_reg,
- rdev->desc->enable_mask, 0);
+ return regmap_update_bits(pmic->map, rdev->desc->enable_reg,
+ rdev->desc->enable_mask, 0);
}
static int hi6421_spmi_regulator_get_voltage_sel(struct regulator_dev *rdev)
struct hi6421_spmi_pmic *pmic = sreg->pmic;
u32 reg_val;
- reg_val = hi6421_spmi_pmic_read(pmic, rdev->desc->vsel_reg);
+ regmap_read(pmic->map, rdev->desc->vsel_reg, ®_val);
return (reg_val & rdev->desc->vsel_mask) >> (ffs(rdev->desc->vsel_mask) - 1);
}
reg_val = selector << (ffs(rdev->desc->vsel_mask) - 1);
/* set voltage selector */
- return hi6421_spmi_pmic_rmw(pmic, rdev->desc->vsel_reg,
- rdev->desc->vsel_mask, reg_val);
+ return regmap_update_bits(pmic->map, rdev->desc->vsel_reg,
+ rdev->desc->vsel_mask, reg_val);
}
static unsigned int hi6421_spmi_regulator_get_mode(struct regulator_dev *rdev)
struct hi6421_spmi_pmic *pmic = sreg->pmic;
u32 reg_val;
- reg_val = hi6421_spmi_pmic_read(pmic, rdev->desc->enable_reg);
+ regmap_read(pmic->map, rdev->desc->enable_reg, ®_val);
if (reg_val & sreg->eco_mode_mask)
return REGULATOR_MODE_IDLE;
return -EINVAL;
}
- return hi6421_spmi_pmic_rmw(pmic, rdev->desc->enable_reg,
- sreg->eco_mode_mask, val);
+ return regmap_update_bits(pmic->map, rdev->desc->enable_reg,
+ sreg->eco_mode_mask, val);
}
static unsigned int
config.dev = pdev->dev.parent;
config.driver_data = sreg;
+ config.regmap = pmic->map;
rdev = devm_regulator_register(dev, &info->desc, &config);
if (IS_ERR(rdev)) {