drm/i915: Remove bogus ips_enabled check.

The flag just tells us IPS can be enabled, if the primary plane
is not enabled it means IPS might not be. This never triggered
in CI because we don't have a haswell ULT there, but can be
reproduced easily with kms_atomic_transitions.plane-all-modeset-transition

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171110113503.16253-2-maarten.lankhorst@linux.intel.com
[mlankhorst: Remove from haswell_get_pipe_config too. (danvet)]
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 63c8b9c..2ecdd20 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9233,10 +9233,6 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
                        ironlake_get_pfit_config(crtc, pipe_config);
        }
 
-       if (IS_HASWELL(dev_priv))
-               pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
-                       (I915_READ(IPS_CTL) & IPS_ENABLE);
-
        if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
            !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
                pipe_config->pixel_multiplier =
@@ -11259,10 +11255,6 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
                PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
        }
 
-       /* BDW+ don't expose a synchronous way to read the state */
-       if (IS_HASWELL(dev_priv))
-               PIPE_CONF_CHECK_I(ips_enabled);
-
        PIPE_CONF_CHECK_I(double_wide);
 
        PIPE_CONF_CHECK_P(shared_dpll);