+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Display DSI 10nm PHY
-
-maintainers:
- - Krishna Manikandan <quic_mkrishn@quicinc.com>
-
-allOf:
- - $ref: dsi-phy-common.yaml#
-
-properties:
- compatible:
- enum:
- - qcom,dsi-phy-10nm
- - qcom,dsi-phy-10nm-8998
-
- reg:
- items:
- - description: dsi phy register set
- - description: dsi phy lane register set
- - description: dsi pll register set
-
- reg-names:
- items:
- - const: dsi_phy
- - const: dsi_phy_lane
- - const: dsi_pll
-
- vdds-supply:
- description: |
- Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
- connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
-
- qcom,phy-rescode-offset-top:
- $ref: /schemas/types.yaml#/definitions/int8-array
- maxItems: 5
- description:
- Integer array of offset for pull-up legs rescode for all five lanes.
- To offset the drive strength from the calibrated value in an increasing
- manner, -32 is the weakest and +31 is the strongest.
- items:
- minimum: -32
- maximum: 31
-
- qcom,phy-rescode-offset-bot:
- $ref: /schemas/types.yaml#/definitions/int8-array
- maxItems: 5
- description:
- Integer array of offset for pull-down legs rescode for all five lanes.
- To offset the drive strength from the calibrated value in a decreasing
- manner, -32 is the weakest and +31 is the strongest.
- items:
- minimum: -32
- maximum: 31
-
- qcom,phy-drive-ldo-level:
- $ref: /schemas/types.yaml#/definitions/uint32
- description:
- The PHY LDO has an amplitude tuning feature to adjust the LDO output
- for the HSTX drive. Use supported levels (mV) to offset the drive level
- from the default value.
- enum: [ 375, 400, 425, 450, 475, 500 ]
-
-required:
- - compatible
- - reg
- - reg-names
-
-unevaluatedProperties: false
-
-examples:
- - |
- #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
- #include <dt-bindings/clock/qcom,rpmh.h>
-
- dsi-phy@ae94400 {
- compatible = "qcom,dsi-phy-10nm";
- reg = <0x0ae94400 0x200>,
- <0x0ae94600 0x280>,
- <0x0ae94a00 0x1e0>;
- reg-names = "dsi_phy",
- "dsi_phy_lane",
- "dsi_pll";
-
- #clock-cells = <1>;
- #phy-cells = <0>;
-
- vdds-supply = <&vdda_mipi_dsi0_pll>;
- clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
- <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "iface", "ref";
-
- qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
- qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
- qcom,phy-drive-ldo-level = <400>;
- };
-...
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Display DSI 14nm PHY
-
-maintainers:
- - Krishna Manikandan <quic_mkrishn@quicinc.com>
-
-allOf:
- - $ref: dsi-phy-common.yaml#
-
-properties:
- compatible:
- enum:
- - qcom,dsi-phy-14nm
- - qcom,dsi-phy-14nm-2290
- - qcom,dsi-phy-14nm-660
- - qcom,dsi-phy-14nm-8953
- - qcom,sm6125-dsi-phy-14nm
- - qcom,sm6150-dsi-phy-14nm
-
- reg:
- items:
- - description: dsi phy register set
- - description: dsi phy lane register set
- - description: dsi pll register set
-
- reg-names:
- items:
- - const: dsi_phy
- - const: dsi_phy_lane
- - const: dsi_pll
-
- vcca-supply:
- description: Phandle to vcca regulator device node.
-
- power-domains:
- description:
- A phandle and PM domain specifier for an optional power domain.
- maxItems: 1
-
- required-opps:
- description:
- A phandle to an OPP node describing the power domain's performance point.
- maxItems: 1
-
-required:
- - compatible
- - reg
- - reg-names
-
-unevaluatedProperties: false
-
-examples:
- - |
- #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
- #include <dt-bindings/clock/qcom,rpmh.h>
-
- dsi-phy@ae94400 {
- compatible = "qcom,dsi-phy-14nm";
- reg = <0x0ae94400 0x200>,
- <0x0ae94600 0x280>,
- <0x0ae94a00 0x1e0>;
- reg-names = "dsi_phy",
- "dsi_phy_lane",
- "dsi_pll";
-
- #clock-cells = <1>;
- #phy-cells = <0>;
-
- vcca-supply = <&vcca_reg>;
- clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
- <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "iface", "ref";
- };
-...
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Display DSI 20nm PHY
-
-maintainers:
- - Krishna Manikandan <quic_mkrishn@quicinc.com>
-
-allOf:
- - $ref: dsi-phy-common.yaml#
-
-properties:
- compatible:
- const: qcom,dsi-phy-20nm
-
- reg:
- items:
- - description: dsi pll register set
- - description: dsi phy register set
- - description: dsi phy regulator register set
-
- reg-names:
- items:
- - const: dsi_pll
- - const: dsi_phy
- - const: dsi_phy_regulator
-
- vcca-supply:
- description: Phandle to vcca regulator device node.
-
- vddio-supply:
- description: Phandle to vdd-io regulator device node.
-
-required:
- - compatible
- - reg
- - reg-names
- - vddio-supply
- - vcca-supply
-
-unevaluatedProperties: false
-
-examples:
- - |
- #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
- #include <dt-bindings/clock/qcom,rpmh.h>
-
- dsi-phy@fd922a00 {
- compatible = "qcom,dsi-phy-20nm";
- reg = <0xfd922a00 0xd4>,
- <0xfd922b00 0x2b0>,
- <0xfd922d80 0x7b>;
- reg-names = "dsi_pll",
- "dsi_phy",
- "dsi_phy_regulator";
-
- #clock-cells = <1>;
- #phy-cells = <0>;
-
- vcca-supply = <&vcca_reg>;
- vddio-supply = <&vddio_reg>;
-
- clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
- <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "iface", "ref";
- };
-...
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Display DSI 28nm PHY
-
-maintainers:
- - Krishna Manikandan <quic_mkrishn@quicinc.com>
-
-allOf:
- - $ref: dsi-phy-common.yaml#
-
-properties:
- compatible:
- enum:
- - qcom,dsi-phy-28nm-8226
- - qcom,dsi-phy-28nm-8937
- - qcom,dsi-phy-28nm-8960
- - qcom,dsi-phy-28nm-hpm
- - qcom,dsi-phy-28nm-hpm-fam-b
- - qcom,dsi-phy-28nm-lp
-
- reg:
- items:
- - description: dsi pll register set
- - description: dsi phy register set
- - description: dsi phy regulator register set
-
- reg-names:
- items:
- - const: dsi_pll
- - const: dsi_phy
- - const: dsi_phy_regulator
-
- vddio-supply:
- description: Phandle to vdd-io regulator device node.
-
- qcom,dsi-phy-regulator-ldo-mode:
- type: boolean
- description: Indicates if the LDO mode PHY regulator is wanted.
-
-required:
- - compatible
- - reg
- - reg-names
- - vddio-supply
-
-unevaluatedProperties: false
-
-examples:
- - |
- #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
- #include <dt-bindings/clock/qcom,rpmh.h>
-
- dsi-phy@fd922a00 {
- compatible = "qcom,dsi-phy-28nm-lp";
- reg = <0xfd922a00 0xd4>,
- <0xfd922b00 0x2b0>,
- <0xfd922d80 0x7b>;
- reg-names = "dsi_pll",
- "dsi_phy",
- "dsi_phy_regulator";
-
- #clock-cells = <1>;
- #phy-cells = <0>;
-
- vddio-supply = <&vddio_reg>;
-
- clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
- <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "iface", "ref";
- };
-...
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Display DSI 7nm PHY
-
-maintainers:
- - Jonathan Marek <jonathan@marek.ca>
-
-allOf:
- - $ref: dsi-phy-common.yaml#
-
-properties:
- compatible:
- oneOf:
- - items:
- - enum:
- - qcom,dsi-phy-7nm
- - qcom,dsi-phy-7nm-8150
- - qcom,kaanapali-dsi-phy-3nm
- - qcom,sa8775p-dsi-phy-5nm
- - qcom,sar2130p-dsi-phy-5nm
- - qcom,sc7280-dsi-phy-7nm
- - qcom,sm6375-dsi-phy-7nm
- - qcom,sm8350-dsi-phy-5nm
- - qcom,sm8450-dsi-phy-5nm
- - qcom,sm8550-dsi-phy-4nm
- - qcom,sm8650-dsi-phy-4nm
- - qcom,sm8750-dsi-phy-3nm
- - items:
- - enum:
- - qcom,eliza-dsi-phy-4nm
- - const: qcom,sm8650-dsi-phy-4nm
- - items:
- - enum:
- - qcom,qcs8300-dsi-phy-5nm
- - qcom,sc8280xp-dsi-phy-5nm
- - const: qcom,sa8775p-dsi-phy-5nm
-
- reg:
- items:
- - description: dsi phy register set
- - description: dsi phy lane register set
- - description: dsi pll register set
-
- reg-names:
- items:
- - const: dsi_phy
- - const: dsi_phy_lane
- - const: dsi_pll
-
- vdds-supply:
- description: |
- Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150)
-
- phy-type:
- description: D-PHY (default) or C-PHY mode
- enum: [ 10, 11 ]
- default: 10
-
-required:
- - compatible
- - reg
- - reg-names
-
-unevaluatedProperties: false
-
-examples:
- - |
- #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
- #include <dt-bindings/clock/qcom,rpmh.h>
-
- dsi-phy@ae94400 {
- compatible = "qcom,dsi-phy-7nm";
- reg = <0x0ae94400 0x200>,
- <0x0ae94600 0x280>,
- <0x0ae94900 0x260>;
- reg-names = "dsi_phy",
- "dsi_phy_lane",
- "dsi_pll";
-
- #clock-cells = <1>;
- #phy-cells = <0>;
-
- vdds-supply = <&vreg_l5a_0p88>;
- clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
- <&rpmhcc RPMH_CXO_CLK>;
- clock-names = "iface", "ref";
- };
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/msm/dsi-phy-common.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Display DSI PHY Common Properties
-
-maintainers:
- - Krishna Manikandan <quic_mkrishn@quicinc.com>
-
-description:
- Common properties for Qualcomm Display DSI PHY.
-
-properties:
- "#clock-cells":
- const: 1
- description:
- See include/dt-bindings/clock/qcom,dsi-phy-28nm.h for clock IDs.
-
- "#phy-cells":
- const: 0
-
- clocks:
- items:
- - description: Display AHB clock
- - description: Board XO source
-
- clock-names:
- items:
- - const: iface
- - const: ref
-
-required:
- - clocks
- - clock-names
- - "#clock-cells"
- - "#phy-cells"
-
-additionalProperties: true
-...
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-10nm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DSI 10nm PHY
+
+maintainers:
+ - Krishna Manikandan <quic_mkrishn@quicinc.com>
+
+allOf:
+ - $ref: qcom,dsi-phy-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - qcom,dsi-phy-10nm
+ - qcom,dsi-phy-10nm-8998
+
+ reg:
+ items:
+ - description: dsi phy register set
+ - description: dsi phy lane register set
+ - description: dsi pll register set
+
+ reg-names:
+ items:
+ - const: dsi_phy
+ - const: dsi_phy_lane
+ - const: dsi_pll
+
+ vdds-supply:
+ description: |
+ Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
+ connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
+
+ qcom,phy-rescode-offset-top:
+ $ref: /schemas/types.yaml#/definitions/int8-array
+ maxItems: 5
+ description:
+ Integer array of offset for pull-up legs rescode for all five lanes.
+ To offset the drive strength from the calibrated value in an increasing
+ manner, -32 is the weakest and +31 is the strongest.
+ items:
+ minimum: -32
+ maximum: 31
+
+ qcom,phy-rescode-offset-bot:
+ $ref: /schemas/types.yaml#/definitions/int8-array
+ maxItems: 5
+ description:
+ Integer array of offset for pull-down legs rescode for all five lanes.
+ To offset the drive strength from the calibrated value in a decreasing
+ manner, -32 is the weakest and +31 is the strongest.
+ items:
+ minimum: -32
+ maximum: 31
+
+ qcom,phy-drive-ldo-level:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The PHY LDO has an amplitude tuning feature to adjust the LDO output
+ for the HSTX drive. Use supported levels (mV) to offset the drive level
+ from the default value.
+ enum: [ 375, 400, 425, 450, 475, 500 ]
+
+required:
+ - compatible
+ - reg
+ - reg-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ dsi-phy@ae94400 {
+ compatible = "qcom,dsi-phy-10nm";
+ reg = <0x0ae94400 0x200>,
+ <0x0ae94600 0x280>,
+ <0x0ae94a00 0x1e0>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ vdds-supply = <&vdda_mipi_dsi0_pll>;
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+
+ qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
+ qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
+ qcom,phy-drive-ldo-level = <400>;
+ };
+...
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-14nm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DSI 14nm PHY
+
+maintainers:
+ - Krishna Manikandan <quic_mkrishn@quicinc.com>
+
+allOf:
+ - $ref: qcom,dsi-phy-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - qcom,dsi-phy-14nm
+ - qcom,dsi-phy-14nm-2290
+ - qcom,dsi-phy-14nm-660
+ - qcom,dsi-phy-14nm-8953
+ - qcom,sm6125-dsi-phy-14nm
+ - qcom,sm6150-dsi-phy-14nm
+
+ reg:
+ items:
+ - description: dsi phy register set
+ - description: dsi phy lane register set
+ - description: dsi pll register set
+
+ reg-names:
+ items:
+ - const: dsi_phy
+ - const: dsi_phy_lane
+ - const: dsi_pll
+
+ vcca-supply:
+ description: Phandle to vcca regulator device node.
+
+ power-domains:
+ description:
+ A phandle and PM domain specifier for an optional power domain.
+ maxItems: 1
+
+ required-opps:
+ description:
+ A phandle to an OPP node describing the power domain's performance point.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ dsi-phy@ae94400 {
+ compatible = "qcom,dsi-phy-14nm";
+ reg = <0x0ae94400 0x200>,
+ <0x0ae94600 0x280>,
+ <0x0ae94a00 0x1e0>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ vcca-supply = <&vcca_reg>;
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
+...
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-20nm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DSI 20nm PHY
+
+maintainers:
+ - Krishna Manikandan <quic_mkrishn@quicinc.com>
+
+allOf:
+ - $ref: qcom,dsi-phy-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,dsi-phy-20nm
+
+ reg:
+ items:
+ - description: dsi pll register set
+ - description: dsi phy register set
+ - description: dsi phy regulator register set
+
+ reg-names:
+ items:
+ - const: dsi_pll
+ - const: dsi_phy
+ - const: dsi_phy_regulator
+
+ vcca-supply:
+ description: Phandle to vcca regulator device node.
+
+ vddio-supply:
+ description: Phandle to vdd-io regulator device node.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - vddio-supply
+ - vcca-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ dsi-phy@fd922a00 {
+ compatible = "qcom,dsi-phy-20nm";
+ reg = <0xfd922a00 0xd4>,
+ <0xfd922b00 0x2b0>,
+ <0xfd922d80 0x7b>;
+ reg-names = "dsi_pll",
+ "dsi_phy",
+ "dsi_phy_regulator";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ vcca-supply = <&vcca_reg>;
+ vddio-supply = <&vddio_reg>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
+...
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-28nm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DSI 28nm PHY
+
+maintainers:
+ - Krishna Manikandan <quic_mkrishn@quicinc.com>
+
+allOf:
+ - $ref: qcom,dsi-phy-common.yaml#
+
+properties:
+ compatible:
+ enum:
+ - qcom,dsi-phy-28nm-8226
+ - qcom,dsi-phy-28nm-8937
+ - qcom,dsi-phy-28nm-8960
+ - qcom,dsi-phy-28nm-hpm
+ - qcom,dsi-phy-28nm-hpm-fam-b
+ - qcom,dsi-phy-28nm-lp
+
+ reg:
+ items:
+ - description: dsi pll register set
+ - description: dsi phy register set
+ - description: dsi phy regulator register set
+
+ reg-names:
+ items:
+ - const: dsi_pll
+ - const: dsi_phy
+ - const: dsi_phy_regulator
+
+ vddio-supply:
+ description: Phandle to vdd-io regulator device node.
+
+ qcom,dsi-phy-regulator-ldo-mode:
+ type: boolean
+ description: Indicates if the LDO mode PHY regulator is wanted.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - vddio-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ dsi-phy@fd922a00 {
+ compatible = "qcom,dsi-phy-28nm-lp";
+ reg = <0xfd922a00 0xd4>,
+ <0xfd922b00 0x2b0>,
+ <0xfd922d80 0x7b>;
+ reg-names = "dsi_pll",
+ "dsi_phy",
+ "dsi_phy_regulator";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ vddio-supply = <&vddio_reg>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
+...
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-7nm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DSI 7nm PHY
+
+maintainers:
+ - Jonathan Marek <jonathan@marek.ca>
+
+allOf:
+ - $ref: qcom,dsi-phy-common.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - qcom,dsi-phy-7nm
+ - qcom,dsi-phy-7nm-8150
+ - qcom,kaanapali-dsi-phy-3nm
+ - qcom,sa8775p-dsi-phy-5nm
+ - qcom,sar2130p-dsi-phy-5nm
+ - qcom,sc7280-dsi-phy-7nm
+ - qcom,sm6375-dsi-phy-7nm
+ - qcom,sm8350-dsi-phy-5nm
+ - qcom,sm8450-dsi-phy-5nm
+ - qcom,sm8550-dsi-phy-4nm
+ - qcom,sm8650-dsi-phy-4nm
+ - qcom,sm8750-dsi-phy-3nm
+ - items:
+ - enum:
+ - qcom,eliza-dsi-phy-4nm
+ - const: qcom,sm8650-dsi-phy-4nm
+ - items:
+ - enum:
+ - qcom,qcs8300-dsi-phy-5nm
+ - qcom,sc8280xp-dsi-phy-5nm
+ - const: qcom,sa8775p-dsi-phy-5nm
+
+ reg:
+ items:
+ - description: dsi phy register set
+ - description: dsi phy lane register set
+ - description: dsi pll register set
+
+ reg-names:
+ items:
+ - const: dsi_phy
+ - const: dsi_phy_lane
+ - const: dsi_pll
+
+ vdds-supply:
+ description: |
+ Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150)
+
+ phy-type:
+ description: D-PHY (default) or C-PHY mode
+ enum: [ 10, 11 ]
+ default: 10
+
+required:
+ - compatible
+ - reg
+ - reg-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ dsi-phy@ae94400 {
+ compatible = "qcom,dsi-phy-7nm";
+ reg = <0x0ae94400 0x200>,
+ <0x0ae94600 0x280>,
+ <0x0ae94900 0x260>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ vdds-supply = <&vreg_l5a_0p88>;
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DSI PHY Common Properties
+
+maintainers:
+ - Krishna Manikandan <quic_mkrishn@quicinc.com>
+
+description:
+ Common properties for Qualcomm Display DSI PHY.
+
+properties:
+ "#clock-cells":
+ const: 1
+ description:
+ See include/dt-bindings/clock/qcom,dsi-phy-28nm.h for clock IDs.
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ items:
+ - description: Display AHB clock
+ - description: Board XO source
+
+ clock-names:
+ items:
+ - const: iface
+ - const: ref
+
+required:
+ - clocks
+ - clock-names
+ - "#clock-cells"
+ - "#phy-cells"
+
+additionalProperties: true
+...
projects / linux-2.6-microblaze.git / commitdiff