drm/amdgpu/mes: Remove idr leftovers v2

Commit
cb17fff3a254 ("drm/amdgpu/mes: remove unused functions")
removed most of the code using these IDRs but forgot to remove the struct
members and init/destroy paths.

There is also interrupt handling code in SDMA 5.0 and 5.2 which appears to
be using it, but is is unreachable since nothing ever allocates the
relevant IDR. We replace those with one time warnings just to avoid any
functional difference, but it is also possible they should be removed.

v2: also fix up gfx_v12_1.c and sdma_v7_1.c

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
References: cb17fff3a254 ("drm/amdgpu/mes: remove unused functions")
Cc: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 6e19836..0d4c77c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -115,9 +115,6 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
 
        adev->mes.adev = adev;
 
-       idr_init(&adev->mes.pasid_idr);
-       idr_init(&adev->mes.gang_id_idr);
-       idr_init(&adev->mes.queue_id_idr);
        ida_init(&adev->mes.doorbell_ida);
        spin_lock_init(&adev->mes.queue_id_lock);
        mutex_init(&adev->mes.mutex_hidden);
@@ -252,9 +249,6 @@ error:
                                              &adev->mes.hung_queue_db_array_cpu_addr[i]);
        }
 
-       idr_destroy(&adev->mes.pasid_idr);
-       idr_destroy(&adev->mes.gang_id_idr);
-       idr_destroy(&adev->mes.queue_id_idr);
        ida_destroy(&adev->mes.doorbell_ida);
        mutex_destroy(&adev->mes.mutex_hidden);
        return r;
@@ -283,9 +277,6 @@ void amdgpu_mes_fini(struct amdgpu_device *adev)
 
        amdgpu_mes_doorbell_free(adev);
 
-       idr_destroy(&adev->mes.pasid_idr);
-       idr_destroy(&adev->mes.gang_id_idr);
-       idr_destroy(&adev->mes.queue_id_idr);
        ida_destroy(&adev->mes.doorbell_ida);
        mutex_destroy(&adev->mes.mutex_hidden);
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index 88685c5..bcf2a06 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -77,9 +77,6 @@ struct amdgpu_mes {
 
        struct mutex                    mutex_hidden;
 
-       struct idr                      pasid_idr;
-       struct idr                      gang_id_idr;
-       struct idr                      queue_id_idr;
        struct ida                      doorbell_ida;
 
        spinlock_t                      queue_id_lock;

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
index 86cc90a..08ae50a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
@@ -30,6 +30,7 @@
 #include "amdgpu_psp.h"
 #include "amdgpu_smu.h"
 #include "amdgpu_atomfirmware.h"
+#include "amdgpu_userq_fence.h"
 #include "imu_v12_1.h"
 #include "soc_v1_0.h"
 #include "gfx_v12_1_pkt.h"
@@ -3602,25 +3603,23 @@ static int gfx_v12_1_eop_irq(struct amdgpu_device *adev,
                             struct amdgpu_irq_src *source,
                             struct amdgpu_iv_entry *entry)
 {
-       int i, xcc_id;
+       u32 doorbell_offset = entry->src_data[0];
        u8 me_id, pipe_id, queue_id;
        struct amdgpu_ring *ring;
-       uint32_t mes_queue_id = entry->src_data[0];
+       int i, xcc_id;
 
        DRM_DEBUG("IH: CP EOP\n");
 
-       if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
-               struct amdgpu_mes_queue *queue;
+       if (adev->enable_mes && doorbell_offset) {
+               struct amdgpu_userq_fence_driver *fence_drv = NULL;
+               struct xarray *xa = &adev->userq_xa;
+               unsigned long flags;
 
-               mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
-
-               spin_lock(&adev->mes.queue_id_lock);
-               queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
-               if (queue) {
-                       DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
-                       amdgpu_fence_process(queue->ring);
-               }
-               spin_unlock(&adev->mes.queue_id_lock);
+               xa_lock_irqsave(xa, flags);
+               fence_drv = xa_load(xa, doorbell_offset);
+               if (fence_drv)
+                       amdgpu_userq_fence_driver_process(fence_drv);
+               xa_unlock_irqrestore(xa, flags);
        } else {
                me_id = (entry->ring_id & 0x0c) >> 2;
                pipe_id = (entry->ring_id & 0x03) >> 0;

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 7811cbb..e77e079 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1704,24 +1704,12 @@ static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev,
                                      struct amdgpu_irq_src *source,
                                      struct amdgpu_iv_entry *entry)
 {
-       uint32_t mes_queue_id = entry->src_data[0];
-
        DRM_DEBUG("IH: SDMA trap\n");
 
-       if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
-               struct amdgpu_mes_queue *queue;
-
-               mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
-
-               spin_lock(&adev->mes.queue_id_lock);
-               queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
-               if (queue) {
-                       DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
-                       amdgpu_fence_process(queue->ring);
-               }
-               spin_unlock(&adev->mes.queue_id_lock);
+       if (drm_WARN_ON_ONCE(&adev->ddev,
+                            adev->enable_mes &&
+                            (entry->src_data[0] & AMDGPU_FENCE_MES_QUEUE_FLAG)))
                return 0;
-       }
 
        switch (entry->client_id) {
        case SOC15_IH_CLIENTID_SDMA0:

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index dbe5b8f..50b5196 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1617,24 +1617,12 @@ static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
                                      struct amdgpu_irq_src *source,
                                      struct amdgpu_iv_entry *entry)
 {
-       uint32_t mes_queue_id = entry->src_data[0];
-
        DRM_DEBUG("IH: SDMA trap\n");
 
-       if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
-               struct amdgpu_mes_queue *queue;
-
-               mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
-
-               spin_lock(&adev->mes.queue_id_lock);
-               queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
-               if (queue) {
-                       DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
-                       amdgpu_fence_process(queue->ring);
-               }
-               spin_unlock(&adev->mes.queue_id_lock);
+       if (drm_WARN_ON_ONCE(&adev->ddev,
+                            adev->enable_mes &&
+                            (entry->src_data[0] & AMDGPU_FENCE_MES_QUEUE_FLAG)))
                return 0;
-       }
 
        switch (entry->client_id) {
        case SOC15_IH_CLIENTID_SDMA0:

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
index 5bc45c3..0824cba 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
@@ -1494,24 +1494,13 @@ static int sdma_v7_1_process_trap_irq(struct amdgpu_device *adev,
                                      struct amdgpu_iv_entry *entry)
 {
        int inst, instances, queue, xcc_id = 0;
-       uint32_t mes_queue_id = entry->src_data[0];
 
        DRM_DEBUG("IH: SDMA trap\n");
 
-       if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
-               struct amdgpu_mes_queue *queue;
-
-               mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
-
-               spin_lock(&adev->mes.queue_id_lock);
-               queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
-               if (queue) {
-                       DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
-                       amdgpu_fence_process(queue->ring);
-               }
-               spin_unlock(&adev->mes.queue_id_lock);
+       if (drm_WARN_ON_ONCE(&adev->ddev,
+                            adev->enable_mes &&
+                            (entry->src_data[0] & AMDGPU_FENCE_MES_QUEUE_FLAG)))
                return 0;
-       }
 
        queue = entry->ring_id & 0xf;
        if (adev->gfx.funcs && adev->gfx.funcs->ih_node_to_logical_xcc)