rtw88: 8723d: Add LC calibration
authorPing-Ke Shih <pkshih@realtek.com>
Tue, 12 May 2020 10:26:13 +0000 (18:26 +0800)
committerKalle Valo <kvalo@codeaurora.org>
Wed, 13 May 2020 15:48:41 +0000 (18:48 +0300)
LC calibration is done by hardware circuit. Driver sets the LCK bit to kick
start, and then poll the bit to check if it's done.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20200512102621.5148-2-yhchuang@realtek.com
drivers/net/wireless/realtek/rtw88/main.h
drivers/net/wireless/realtek/rtw88/rtw8723d.c
drivers/net/wireless/realtek/rtw88/rtw8723d.h

index e0365a7..c504698 100644 (file)
@@ -11,6 +11,7 @@
 #include <linux/average.h>
 #include <linux/bitops.h>
 #include <linux/bitfield.h>
+#include <linux/iopoll.h>
 #include <linux/interrupt.h>
 
 #include "util.h"
index 92c742d..0f5ddd4 100644 (file)
@@ -64,6 +64,34 @@ static const struct rtw_hw_reg rtw8723d_txagc[] = {
 #define WLAN_LTR_CTRL1         0xCB004010
 #define WLAN_LTR_CTRL2         0x01233425
 
+static void rtw8723d_lck(struct rtw_dev *rtwdev)
+{
+       u32 lc_cal;
+       u8 val_ctx, rf_val;
+       int ret;
+
+       val_ctx = rtw_read8(rtwdev, REG_CTX);
+       if ((val_ctx & BIT_MASK_CTX_TYPE) != 0)
+               rtw_write8(rtwdev, REG_CTX, val_ctx & ~BIT_MASK_CTX_TYPE);
+       else
+               rtw_write8(rtwdev, REG_TXPAUSE, 0xFF);
+       lc_cal = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK);
+
+       rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal | BIT_LCK);
+
+       ret = read_poll_timeout(rtw_read_rf, rf_val, rf_val != 0x1,
+                               10000, 1000000, false,
+                               rtwdev, RF_PATH_A, RF_CFGCH, BIT_LCK);
+       if (ret)
+               rtw_warn(rtwdev, "failed to poll LCK status bit\n");
+
+       rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal);
+       if ((val_ctx & BIT_MASK_CTX_TYPE) != 0)
+               rtw_write8(rtwdev, REG_CTX, val_ctx);
+       else
+               rtw_write8(rtwdev, REG_TXPAUSE, 0x00);
+}
+
 static void rtw8723d_phy_set_param(struct rtw_dev *rtwdev)
 {
        u8 xtal_cap;
@@ -125,6 +153,9 @@ static void rtw8723d_phy_set_param(struct rtw_dev *rtwdev)
        rtw_phy_init(rtwdev);
 
        rtw_write16_set(rtwdev, REG_TXDMA_OFFSET_CHK, BIT_DROP_DATA_EN);
+
+       rtw8723d_lck(rtwdev);
+
        rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);
        rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20);
 }
index ac66f67..6a7d589 100644 (file)
@@ -78,6 +78,7 @@ struct rtw8723d_efuse {
 #define RFCFGCH_BW_20M         (BIT(11) | BIT(10))
 #define RFCFGCH_BW_40M         BIT(10)
 #define BIT_MASK_RFMOD         BIT(0)
+#define BIT_LCK                        BIT(15)
 
 #define REG_PSDFN              0x0808
 #define REG_ANALOG_P4          0x088c
@@ -115,6 +116,8 @@ struct rtw8723d_efuse {
 #define REG_OFDM_FA_RSTD_11N   0x0d00
 #define BIT_MASK_OFDM_FA_RST1  BIT(27)
 #define BIT_MASK_OFDM_FA_KEEP1 BIT(31)
+#define REG_CTX                        0x0d03
+#define BIT_MASK_CTX_TYPE      GENMASK(6, 4)
 #define REG_OFDM1_CFOTRK       0x0d2c
 #define BIT_EN_CFOTRK          BIT(28)
 #define REG_OFDM1_CSI1         0x0d40