switch (bpc) {
case 6: return 0x2;
case 8: return 0x5;
- case 10: /* fall-through */
+ case 10:
default: return 0x6;
}
}
if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind)
/* untiled */
break;
- /* fall through - tiled memory */
+ fallthrough; /* tiled memory */
case TTM_PL_VRAM:
reg->bus.offset = reg->start << PAGE_SHIFT;
reg->bus.base = device->func->resource_addr(device, 1);
case DRM_MODE_CONNECTOR_VGA:
if (disp->disp.object.oclass < NV50_DISP)
break; /* Can only scale on DFPs. */
- /* Fall-through. */
+ fallthrough;
default:
drm_object_attach_property(&connector->base, dev->mode_config.
scaling_mode_property,
case DCB_OUTPUT_LVDS:
switcheroo_ddc = !!(vga_switcheroo_handler_flags() &
VGA_SWITCHEROO_CAN_SWITCH_DDC);
- /* fall-through */
+ fallthrough;
default:
if (!nv_encoder->i2c)
break;
*/
case 17:
subpack1_high = (raw_frame[16] << 16);
- /* fall through */
+ fallthrough;
case 16:
subpack1_high |= (raw_frame[15] << 8);
- /* fall through */
+ fallthrough;
case 15:
subpack1_high |= raw_frame[14];
- /* fall through */
+ fallthrough;
case 14:
subpack1_low = (raw_frame[13] << 24);
- /* fall through */
+ fallthrough;
case 13:
subpack1_low |= (raw_frame[12] << 16);
- /* fall through */
+ fallthrough;
case 12:
subpack1_low |= (raw_frame[11] << 8);
- /* fall through */
+ fallthrough;
case 11:
subpack1_low |= raw_frame[10];
- /* fall through */
+ fallthrough;
case 10:
subpack0_high = (raw_frame[9] << 16);
- /* fall through */
+ fallthrough;
case 9:
subpack0_high |= (raw_frame[8] << 8);
- /* fall through */
+ fallthrough;
case 8:
subpack0_high |= raw_frame[7];
- /* fall through */
+ fallthrough;
case 7:
subpack0_low = (raw_frame[6] << 24);
- /* fall through */
+ fallthrough;
case 6:
subpack0_low |= (raw_frame[5] << 16);
- /* fall through */
+ fallthrough;
case 5:
subpack0_low |= (raw_frame[4] << 8);
- /* fall through */
+ fallthrough;
case 4:
subpack0_low |= raw_frame[3];
- /* fall through */
+ fallthrough;
case 3:
header = (raw_frame[2] << 16);
- /* fall through */
+ fallthrough;
case 2:
header |= (raw_frame[1] << 8);
- /* fall through */
+ fallthrough;
case 1:
header |= raw_frame[0];
- /* fall through */
+ fallthrough;
case 0:
break;
}
break;
case NV_MEM_ACCESS_WO:
dmaobj->flags0 |= 0x00008000;
- /* fall through */
+ fallthrough;
case NV_MEM_ACCESS_RW:
dmaobj->flags2 |= 0x00000002;
break;
switch (mthd) {
case 0x0000 ... 0x0000: /* subchannel's engine -> software */
nvkm_wr32(device, 0x003280, (engine &= ~mask));
- /* fall through */
+ fallthrough;
case 0x0180 ... 0x01fc: /* handle -> instance */
data = nvkm_rd32(device, 0x003258) & 0x0000ffff;
- /* fall through */
+ fallthrough;
case 0x0100 ... 0x017c:
case 0x0200 ... 0x1ffc: /* pass method down to sw */
if (!(engine & mask) && sw)
case 0x49:
case 0x4b:
nvkm_wr32(device, 0x002230, 0x00000001);
- /* fall through */
+ fallthrough;
case 0x40:
case 0x41:
case 0x42:
outp->dpconf.link_nr = 1;
break;
}
+ fallthrough;
- /* fall-through... */
case DCB_OUTPUT_TMDS:
case DCB_OUTPUT_LVDS:
outp->link = (conf & 0x00000030) >> 4;
switch (*ver) {
case 0x20:
info->mask |= 0x00c0; /* match any link */
- /* fall-through */
+ fallthrough;
case 0x21:
case 0x30:
info->flags = nvbios_rd08(bios, data + 0x05);
break;
case 0x30:
info->script = nvbios_rd16(bios, perf + 0x02);
- /* fall through */
+ fallthrough;
case 0x35:
info->fanspeed = nvbios_rd08(bios, perf + 0x06);
info->voltage = nvbios_rd08(bios, perf + 0x07);
device->chipset == 0xaa ||
device->chipset == 0xac)
return g84_pll_mapping;
- /* fall through */
+ fallthrough;
default:
return NULL;
}
switch (min_t(u8, *hdr, 25)) {
case 25:
p->timing_10_24 = nvbios_rd08(bios, data + 0x18);
- /* fall through */
+ fallthrough;
case 24:
case 23:
case 22:
p->timing_10_21 = nvbios_rd08(bios, data + 0x15);
- /* fall through */
+ fallthrough;
case 21:
p->timing_10_20 = nvbios_rd08(bios, data + 0x14);
- /* fall through */
+ fallthrough;
case 20:
p->timing_10_CWL = nvbios_rd08(bios, data + 0x13);
- /* fall through */
+ fallthrough;
case 19:
p->timing_10_18 = nvbios_rd08(bios, data + 0x12);
- /* fall through */
+ fallthrough;
case 18:
case 17:
p->timing_10_16 = nvbios_rd08(bios, data + 0x10);
case NVKM_CLK_BOOST_NONE:
if (clk->base_khz && freq > clk->base_khz)
return false;
- /* fall through */
+ fallthrough;
case NVKM_CLK_BOOST_BIOS:
if (clk->boost_khz && freq > clk->boost_khz)
return false;
switch (clk->vsrc) {
case nv_clk_src_cclk:
mast |= 0x00400000;
- /* fall through */
+ fallthrough;
default:
nvkm_wr32(device, 0x4600, clk->vdiv);
}
switch (reg) {
case 0x680520:
- shift += 4; /* fall through */
+ shift += 4; fallthrough;
case 0x680508:
- shift += 4; /* fall through */
+ shift += 4; fallthrough;
case 0x680504:
- shift += 4; /* fall through */
+ shift += 4; fallthrough;
case 0x680500:
shift += 4;
}
switch (reg1) {
case 0x680504:
- shift_c040 += 2; /* fall through */
+ shift_c040 += 2; fallthrough;
case 0x680500:
- shift_c040 += 2; /* fall through */
+ shift_c040 += 2; fallthrough;
case 0x680520:
- shift_c040 += 2; /* fall through */
+ shift_c040 += 2; fallthrough;
case 0x680508:
shift_c040 += 2;
}
nvkm_mask(device, 0x00402c, 0xc0771100, ram->ctrl);
nvkm_wr32(device, 0x004048, ram->coef);
nvkm_wr32(device, 0x004030, ram->coef);
- /* fall through */
+ fallthrough;
case 0x43:
case 0x49:
case 0x4b:
nvkm_mask(device, 0x004038, 0xc0771100, ram->ctrl);
nvkm_wr32(device, 0x00403c, ram->coef);
- /* fall through */
+ fallthrough;
default:
nvkm_mask(device, 0x004020, 0xc0771100, ram->ctrl);
nvkm_wr32(device, 0x004024, ram->coef);
break;
case 0x0e: /* eDP, falls through to DPint */
ctx.outp[1] |= 0x00010000;
- /* fall through */
+ fallthrough;
case 0x07: /* DP internal, wtf is this?? HP8670w */
ctx.outp[1] |= 0x00000004; /* use_power_scripts? */
type = DCB_CONNECTOR_eDP;