iommu/mediatek: Add support for Dimensity 1200 MT6893 MM IOMMU

Add support for the two MM IOMMUs found in the MediaTek Dimensity
1200 (MT6893) SoC, used for display, camera, imgsys and vpu.

Since the MT6893 SoC is almost fully compatible with MT8192, also
move the mt8192_larb_region_msk before the newly introduced mt6893
platform data, as the larb regions from mt8192 are fully reused.

Note that the only difference with MT8192 is that MT6893 needs the
SHARE_PGTABLE flag.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Yong Wu <yong.wu@mediatek.com>
Link: https://lore.kernel.org/r/20250410144008.475888-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index df98d0c..0a54c65 100644 (file)
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -1550,6 +1550,31 @@ static const struct mtk_iommu_plat_data mt6795_data = {
        .larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. */
 };
 
+static const unsigned int mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
+       [0] = {~0, ~0},                         /* Region0: larb0/1 */
+       [1] = {0, 0, 0, 0, ~0, ~0, 0, ~0},      /* Region1: larb4/5/7 */
+       [2] = {0, 0, ~0, 0, 0, 0, 0, 0,         /* Region2: larb2/9/11/13/14/16/17/18/19/20 */
+              0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), ~(u32)(BIT(4) | BIT(5)), 0,
+              ~0, ~0, ~0, ~0, ~0},
+       [3] = {0},
+       [4] = {[13] = BIT(9) | BIT(10)},        /* larb13 port9/10 */
+       [5] = {[14] = BIT(4) | BIT(5)},         /* larb14 port4/5 */
+};
+
+static const struct mtk_iommu_plat_data mt6893_data = {
+       .m4u_plat     = M4U_MT8192,
+       .flags        = HAS_BCLK | OUT_ORDER_WR_EN | HAS_SUB_COMM_2BITS |
+                       WR_THROT_EN | IOVA_34_EN | SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
+       .inv_sel_reg  = REG_MMU_INV_SEL_GEN2,
+       .banks_num    = 1,
+       .banks_enable = {true},
+       .iova_region  = mt8192_multi_dom,
+       .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
+       .iova_region_larb_msk = mt8192_larb_region_msk,
+       .larbid_remap    = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
+                           {0, 14, 16}, {0, 13, 18, 17}},
+};
+
 static const struct mtk_iommu_plat_data mt8167_data = {
        .m4u_plat     = M4U_MT8167,
        .flags        = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM,
@@ -1673,17 +1698,6 @@ static const struct mtk_iommu_plat_data mt8188_data_vpp = {
                           27, 28 /* ccu0 */, MTK_INVALID_LARBID}, {4, 6}},
 };
 
-static const unsigned int mt8192_larb_region_msk[MT8192_MULTI_REGION_NR_MAX][MTK_LARB_NR_MAX] = {
-       [0] = {~0, ~0},                         /* Region0: larb0/1 */
-       [1] = {0, 0, 0, 0, ~0, ~0, 0, ~0},      /* Region1: larb4/5/7 */
-       [2] = {0, 0, ~0, 0, 0, 0, 0, 0,         /* Region2: larb2/9/11/13/14/16/17/18/19/20 */
-              0, ~0, 0, ~0, 0, ~(u32)(BIT(9) | BIT(10)), ~(u32)(BIT(4) | BIT(5)), 0,
-              ~0, ~0, ~0, ~0, ~0},
-       [3] = {0},
-       [4] = {[13] = BIT(9) | BIT(10)},        /* larb13 port9/10 */
-       [5] = {[14] = BIT(4) | BIT(5)},         /* larb14 port4/5 */
-};
-
 static const struct mtk_iommu_plat_data mt8192_data = {
        .m4u_plat       = M4U_MT8192,
        .flags          = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
@@ -1777,6 +1791,7 @@ static const struct of_device_id mtk_iommu_of_ids[] = {
        { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
        { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
        { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data},
+       { .compatible = "mediatek.mt6893-iommu-mm", .data = &mt6893_data},
        { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data},
        { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
        { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},