spi: sh-msiof: Correct RX FIFO size for R-Car Gen3

According to the R-Car Gen3 Hardware Manual Errata for Rev 0.55 of
September 28, 2017, the MSIOF receive FIFOs on R-Car Gen3 SoCs have room
for 256 words of 32 bits.

Note that this change has no actual impact on the behavior of the
driver, as SPI_CONTROLLER_MUST_TX is set, and transfer size is currenty
limited to the minimum of the transmit and receive FIFO sizes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/6f74508ea4681aa0b7c6bf6810eab026725e75a3.1747401908.git.geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index 8d18a26..8afb7c1 100644 (file)
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -1108,7 +1108,7 @@ static const struct sh_msiof_chipdata rcar_gen3_data = {
        .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
                              SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
        .tx_fifo_size = 64,
-       .rx_fifo_size = 64,
+       .rx_fifo_size = 256,
        .ctlr_flags = SPI_CONTROLLER_MUST_TX,
        .min_div_pow = 1,
 };
@@ -1117,7 +1117,7 @@ static const struct sh_msiof_chipdata rcar_r8a7795_data = {
        .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
                              SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
        .tx_fifo_size = 64,
-       .rx_fifo_size = 64,
+       .rx_fifo_size = 256,
        .ctlr_flags = SPI_CONTROLLER_MUST_TX,
        .min_div_pow = 1,
        .flags = SH_MSIOF_FLAG_FIXED_DTDL_200,