drm/msm/dpu: add cdm blocks to RM
authorAbhinav Kumar <quic_abhinavk@quicinc.com>
Tue, 12 Dec 2023 20:52:46 +0000 (12:52 -0800)
committerDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Thu, 14 Dec 2023 07:27:23 +0000 (09:27 +0200)
Add the RM APIs necessary to initialize and allocate CDM
blocks to be used by the rest of the DPU pipeline.

changes in v2:
- treat cdm_init() failure as fatal
- fixed the commit text

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/571822/
Link: https://lore.kernel.org/r/20231212205254.12422-9-quic_abhinavk@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

index 0bb28cf..7ed476b 100644 (file)
@@ -8,6 +8,7 @@
 #include "dpu_kms.h"
 #include "dpu_hw_lm.h"
 #include "dpu_hw_ctl.h"
+#include "dpu_hw_cdm.h"
 #include "dpu_hw_pingpong.h"
 #include "dpu_hw_sspp.h"
 #include "dpu_hw_intf.h"
@@ -176,6 +177,18 @@ int dpu_rm_init(struct drm_device *dev,
                rm->hw_sspp[sspp->id - SSPP_NONE] = hw;
        }
 
+       if (cat->cdm) {
+               struct dpu_hw_cdm *hw;
+
+               hw = dpu_hw_cdm_init(dev, cat->cdm, mmio, cat->mdss_ver);
+               if (IS_ERR(hw)) {
+                       rc = PTR_ERR(hw);
+                       DPU_ERROR("failed cdm object creation: err %d\n", rc);
+                       goto fail;
+               }
+               rm->cdm_blk = &hw->base;
+       }
+
        return 0;
 
 fail:
index 36752d8..e3f83eb 100644 (file)
@@ -22,6 +22,7 @@ struct dpu_global_state;
  * @hw_wb: array of wb hardware resources
  * @dspp_blks: array of dspp hardware resources
  * @hw_sspp: array of sspp hardware resources
+ * @cdm_blk: cdm hardware resource
  */
 struct dpu_rm {
        struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
@@ -33,6 +34,7 @@ struct dpu_rm {
        struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
        struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
        struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
+       struct dpu_hw_blk *cdm_blk;
 };
 
 /**