drm/i915/color: move SKL+ gamma and CSC enable read to intel_color
authorJani Nikula <jani.nikula@intel.com>
Thu, 17 Aug 2023 15:53:07 +0000 (18:53 +0300)
committerJani Nikula <jani.nikula@intel.com>
Fri, 25 Aug 2023 10:12:27 +0000 (13:12 +0300)
Abstract the platform specific register access better.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/c0c37c06d1f2673c82d567c8bcbb6b0b0054b5fa.1692287501.git.jani.nikula@intel.com
drivers/gpu/drm/i915/display/intel_color.c
drivers/gpu/drm/i915/display/intel_display.c

index 27331bd..bcc3d99 100644 (file)
@@ -1040,6 +1040,24 @@ static void hsw_get_config(struct intel_crtc_state *crtc_state)
        crtc_state->csc_mode = ilk_read_csc_mode(crtc);
 }
 
+static void skl_get_config(struct intel_crtc_state *crtc_state)
+{
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+       struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+       u32 tmp;
+
+       crtc_state->gamma_mode = hsw_read_gamma_mode(crtc);
+       crtc_state->csc_mode = ilk_read_csc_mode(crtc);
+
+       tmp = intel_de_read(i915, SKL_BOTTOM_COLOR(crtc->pipe));
+
+       if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
+               crtc_state->gamma_enable = true;
+
+       if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
+               crtc_state->csc_enable = true;
+}
+
 static void skl_color_commit_arm(const struct intel_crtc_state *crtc_state)
 {
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -3654,7 +3672,7 @@ static const struct intel_color_funcs tgl_color_funcs = {
        .read_luts = icl_read_luts,
        .lut_equal = icl_lut_equal,
        .read_csc = icl_read_csc,
-       .get_config = hsw_get_config,
+       .get_config = skl_get_config,
 };
 
 static const struct intel_color_funcs icl_color_funcs = {
@@ -3666,7 +3684,7 @@ static const struct intel_color_funcs icl_color_funcs = {
        .read_luts = icl_read_luts,
        .lut_equal = icl_lut_equal,
        .read_csc = icl_read_csc,
-       .get_config = hsw_get_config,
+       .get_config = skl_get_config,
 };
 
 static const struct intel_color_funcs glk_color_funcs = {
@@ -3677,7 +3695,7 @@ static const struct intel_color_funcs glk_color_funcs = {
        .read_luts = glk_read_luts,
        .lut_equal = glk_lut_equal,
        .read_csc = skl_read_csc,
-       .get_config = hsw_get_config,
+       .get_config = skl_get_config,
 };
 
 static const struct intel_color_funcs skl_color_funcs = {
@@ -3688,7 +3706,7 @@ static const struct intel_color_funcs skl_color_funcs = {
        .read_luts = bdw_read_luts,
        .lut_equal = ivb_lut_equal,
        .read_csc = skl_read_csc,
-       .get_config = hsw_get_config,
+       .get_config = skl_get_config,
 };
 
 static const struct intel_color_funcs bdw_color_funcs = {
index 0c56d35..cbe5db8 100644 (file)
@@ -60,7 +60,6 @@
 #include "intel_cdclk.h"
 #include "intel_clock_gating.h"
 #include "intel_color.h"
-#include "intel_color_regs.h"
 #include "intel_crt.h"
 #include "intel_crtc.h"
 #include "intel_crtc_state_dump.h"
@@ -3732,17 +3731,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
 
        pipe_config->sink_format = pipe_config->output_format;
 
-       if (DISPLAY_VER(dev_priv) >= 9) {
-               tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
-
-               if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
-                       pipe_config->gamma_enable = true;
-
-               if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
-                       pipe_config->csc_enable = true;
-       } else {
+       if (DISPLAY_VER(dev_priv) < 9)
                i9xx_get_pipe_color_config(pipe_config);
-       }
 
        intel_color_get_config(pipe_config);