clk: tegra20: Reparent dsi clock to pll_d_out0

Reparent DSI clock to PLLD_OUT0 instead of directly descend from PLLD.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 2c58ce2..c606c2b 100644 (file)
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -802,9 +802,9 @@ static void __init tegra20_periph_clk_init(void)
        clks[TEGRA20_CLK_MC] = clk;
 
        /* dsi */
-       clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
-                                   48, periph_clk_enb_refcnt);
-       clk_register_clkdev(clk, NULL, "dsi");
+       clk = tegra_clk_register_periph_gate("dsi", "pll_d_out0", 0,
+                                            clk_base, 0, TEGRA20_CLK_DSI,
+                                            periph_clk_enb_refcnt);
        clks[TEGRA20_CLK_DSI] = clk;
 
        /* pex */