drm/amdgpu/vcn2.5: fix DPG mode power off issue on instance 1
authorJames Zhu <James.Zhu@amd.com>
Wed, 5 Feb 2020 14:20:22 +0000 (09:20 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 11 Feb 2020 20:10:36 +0000 (15:10 -0500)
Support pause_state for multiple instance, and it will fix vcn2.5 DPG mode
power off issue on instance 1.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c

index d6deb0e..6fe0573 100644 (file)
@@ -179,6 +179,7 @@ struct amdgpu_vcn_inst {
        struct amdgpu_irq_src   irq;
        struct amdgpu_vcn_reg   external;
        struct amdgpu_bo        *dpg_sram_bo;
+       struct dpg_pause_state  pause_state;
        void                    *dpg_sram_cpu_addr;
        uint64_t                dpg_sram_gpu_addr;
        uint32_t                *dpg_sram_curr_addr;
@@ -190,8 +191,6 @@ struct amdgpu_vcn {
        const struct firmware   *fw;    /* VCN firmware */
        unsigned                num_enc_rings;
        enum amd_powergating_state cur_state;
-       struct dpg_pause_state pause_state;
-
        bool                    indirect_sram;
 
        uint8_t num_vcn_inst;
index 1a24fad..71f61af 100644 (file)
@@ -1207,9 +1207,10 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
        struct amdgpu_ring *ring;
 
        /* pause/unpause if state is changed */
-       if (adev->vcn.pause_state.fw_based != new_state->fw_based) {
+       if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
                DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
-                       adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg,
+                       adev->vcn.inst[inst_idx].pause_state.fw_based,
+                       adev->vcn.inst[inst_idx].pause_state.jpeg,
                        new_state->fw_based, new_state->jpeg);
 
                reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
@@ -1258,13 +1259,14 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
                        reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
                        WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
                }
-               adev->vcn.pause_state.fw_based = new_state->fw_based;
+               adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
        }
 
        /* pause/unpause if state is changed */
-       if (adev->vcn.pause_state.jpeg != new_state->jpeg) {
+       if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) {
                DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
-                       adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg,
+                       adev->vcn.inst[inst_idx].pause_state.fw_based,
+                       adev->vcn.inst[inst_idx].pause_state.jpeg,
                        new_state->fw_based, new_state->jpeg);
 
                reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
@@ -1318,7 +1320,7 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
                        reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
                        WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
                }
-               adev->vcn.pause_state.jpeg = new_state->jpeg;
+               adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg;
        }
 
        return 0;
index 4f72167..c387c81 100644 (file)
@@ -1137,9 +1137,9 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
        int ret_code;
 
        /* pause/unpause if state is changed */
-       if (adev->vcn.pause_state.fw_based != new_state->fw_based) {
+       if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
                DRM_DEBUG("dpg pause state changed %d -> %d",
-                       adev->vcn.pause_state.fw_based, new_state->fw_based);
+                       adev->vcn.inst[inst_idx].pause_state.fw_based,  new_state->fw_based);
                reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
                        (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
 
@@ -1185,7 +1185,7 @@ static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
                        reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
                        WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
                }
-               adev->vcn.pause_state.fw_based = new_state->fw_based;
+               adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
        }
 
        return 0;
index 70fae79..97ab44c 100644 (file)
@@ -1367,9 +1367,9 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
        int ret_code;
 
        /* pause/unpause if state is changed */
-       if (adev->vcn.pause_state.fw_based != new_state->fw_based) {
+       if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
                DRM_DEBUG("dpg pause state changed %d -> %d",
-                       adev->vcn.pause_state.fw_based, new_state->fw_based);
+                       adev->vcn.inst[inst_idx].pause_state.fw_based,  new_state->fw_based);
                reg_data = RREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE) &
                        (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
 
@@ -1414,7 +1414,7 @@ static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
                        reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
                        WREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE, reg_data);
                }
-               adev->vcn.pause_state.fw_based = new_state->fw_based;
+               adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
        }
 
        return 0;