drm/amdgpu: Remove volatile from ring manipulation
authorRodrigo Siqueira <siqueira@igalia.com>
Mon, 8 Sep 2025 23:15:38 +0000 (17:15 -0600)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 15 Sep 2025 20:51:15 +0000 (16:51 -0400)
None of the pointer operations handled by the ring file requires
volatile, for this reason, this commit removes all occurrences of
volatile associated with rings.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

index 17848ce..6d12317 100644 (file)
@@ -545,7 +545,7 @@ struct amdgpu_wb {
         * this value can be accessed directly by using the offset as an index.
         * For the GPU address, it is necessary to use gpu_addr and the offset.
         */
-       volatile uint32_t       *wb;
+       uint32_t                *wb;
 
        /**
         * @gpu_addr:
index 7670f5d..80b8554 100644 (file)
@@ -114,7 +114,7 @@ struct amdgpu_sched {
  */
 struct amdgpu_fence_driver {
        uint64_t                        gpu_addr;
-       volatile uint32_t               *cpu_addr;
+       uint32_t                        *cpu_addr;
        /* sync_seq is protected by ring emission lock */
        uint32_t                        sync_seq;
        atomic_t                        last_seq;
@@ -298,7 +298,7 @@ struct amdgpu_ring {
        unsigned int            ring_backup_entries_to_copy;
        unsigned                rptr_offs;
        u64                     rptr_gpu_addr;
-       volatile u32            *rptr_cpu_addr;
+       u32                     *rptr_cpu_addr;
 
        /**
         * @wptr:
@@ -378,19 +378,19 @@ struct amdgpu_ring {
         * This is the CPU address pointer in the writeback slot. This is used
         * to commit changes to the GPU.
         */
-       volatile u32            *wptr_cpu_addr;
+       u32                     *wptr_cpu_addr;
        unsigned                fence_offs;
        u64                     fence_gpu_addr;
-       volatile u32            *fence_cpu_addr;
+       u32                     *fence_cpu_addr;
        uint64_t                current_ctx;
        char                    name[16];
        u32                     trail_seq;
        unsigned                trail_fence_offs;
        u64                     trail_fence_gpu_addr;
-       volatile u32            *trail_fence_cpu_addr;
+       u32                     *trail_fence_cpu_addr;
        unsigned                cond_exe_offs;
        u64                     cond_exe_gpu_addr;
-       volatile u32            *cond_exe_cpu_addr;
+       u32                     *cond_exe_cpu_addr;
        unsigned int            set_q_mode_offs;
        u32                     *set_q_mode_ptr;
        u64                     set_q_mode_token;
index f6ac6a3..8841d72 100644 (file)
@@ -4075,7 +4075,7 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
        struct dma_fence *f = NULL;
        unsigned int index;
        uint64_t gpu_addr;
-       volatile uint32_t *cpu_ptr;
+       uint32_t *cpu_ptr;
        long r;
 
        memset(&ib, 0, sizeof(ib));
index ff600a6..86b3fca 100644 (file)
@@ -603,7 +603,7 @@ static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
        struct dma_fence *f = NULL;
        unsigned index;
        uint64_t gpu_addr;
-       volatile uint32_t *cpu_ptr;
+       uint32_t *cpu_ptr;
        long r;
 
        /* MES KIQ fw hasn't indirect buffer support for now */
index a14fd94..710ec9c 100644 (file)
@@ -497,7 +497,7 @@ static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
        struct dma_fence *f = NULL;
        unsigned index;
        uint64_t gpu_addr;
-       volatile uint32_t *cpu_ptr;
+       uint32_t *cpu_ptr;
        long r;
 
        /* MES KIQ fw hasn't indirect buffer support for now */