ARM: tegra: apalis-tk1: reorder host1x/hdmi properties
authorMarcel Ziswiler <marcel.ziswiler@toradex.com>
Sat, 1 Sep 2018 13:04:47 +0000 (15:04 +0200)
committerThierry Reding <treding@nvidia.com>
Wed, 26 Sep 2018 14:50:34 +0000 (16:50 +0200)
Reorder Host1x/HDMI properties.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
arch/arm/boot/dts/tegra124-apalis.dtsi

index 09e3641..86768ba 100644 (file)
 
        host1x@50000000 {
                hdmi@54280000 {
-                       pll-supply = <&reg_1v05_avdd_hdmi_pll>;
-                       vdd-supply = <&reg_3v3_avdd_hdmi>;
                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
                        nvidia,hpd-gpio =
                                <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+                       pll-supply = <&reg_1v05_avdd_hdmi_pll>;
+                       vdd-supply = <&reg_3v3_avdd_hdmi>;
                };
        };
 
index 5e7ae5e..2c291d2 100644 (file)
 
        host1x@50000000 {
                hdmi@54280000 {
-                       pll-supply = <&reg_1v05_avdd_hdmi_pll>;
-                       vdd-supply = <&reg_3v3_avdd_hdmi>;
                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
                        nvidia,hpd-gpio =
                                <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+                       pll-supply = <&reg_1v05_avdd_hdmi_pll>;
+                       vdd-supply = <&reg_3v3_avdd_hdmi>;
                };
        };