arm64: dts: freescale: Fix SP805 clock-names

The SP805 binding sets the order of the clock-names to be: "wdog_clk",
"apb_pclk" (in exactly that order).

Change the order in the DTs for Freescale platforms to match that. The
two clocks given in all nodes are actually the same, so that does not
change any behaviour.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 0efeb8f..13c0163 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -722,14 +722,14 @@
                        compatible = "arm,sp805", "arm,primecell";
                        reg = <0x0 0xc000000 0x0 0x1000>;
                        clocks = <&clockgen 4 15>, <&clockgen 4 15>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster1_core1_watchdog: watchdog@c010000 {
                        compatible = "arm,sp805", "arm,primecell";
                        reg = <0x0 0xc010000 0x0 0x1000>;
                        clocks = <&clockgen 4 15>, <&clockgen 4 15>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                sai1: audio-controller@f100000 {

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index b961a89..c909ad1 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -676,56 +676,56 @@
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc000000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster1_core1_watchdog: wdt@c010000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc010000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster1_core2_watchdog: wdt@c020000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc020000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster1_core3_watchdog: wdt@c030000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc030000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster2_core0_watchdog: wdt@c100000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc100000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster2_core1_watchdog: wdt@c110000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc110000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster2_core2_watchdog: wdt@c120000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc120000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster2_core3_watchdog: wdt@c130000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc130000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                fsl_mc: fsl-mc@80c000000 {

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index cc36c96..bf72918 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -354,56 +354,56 @@
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc000000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster1_core1_watchdog: wdt@c010000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc010000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster2_core0_watchdog: wdt@c100000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc100000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster2_core1_watchdog: wdt@c110000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc110000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster3_core0_watchdog: wdt@c200000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc200000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster3_core1_watchdog: wdt@c210000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc210000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster4_core0_watchdog: wdt@c300000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc300000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                cluster4_core1_watchdog: wdt@c310000 {
                        compatible = "arm,sp805-wdt", "arm,primecell";
                        reg = <0x0 0xc310000 0x0 0x1000>;
                        clocks = <&clockgen 4 3>, <&clockgen 4 3>;
-                       clock-names = "apb_pclk", "wdog_clk";
+                       clock-names = "wdog_clk", "apb_pclk";
                };
 
                crypto: crypto@8000000 {