drm/amd/display: add DST_Y_DELTA_DRQ_LIMIT hw programming

[why]
dchubp needs to program DST_Y_DELTA_DRQ_LIMIT  based on dml2.x

Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
index 57de984..94730f3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c
@@ -580,7 +580,56 @@ static bool hubp42_program_surface_flip_and_addr(
 
        return true;
 }
+void hubp42_setup_interdependent(
+               struct hubp *hubp,
+               struct dml2_dchub_per_pipe_register_set *pipe_regs)
+{
+       struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
+
+       REG_SET_2(PREFETCH_SETTINGS, 0,
+                       DST_Y_PREFETCH, pipe_regs->dlg_regs.dst_y_prefetch,
+                       VRATIO_PREFETCH, pipe_regs->dlg_regs.vratio_prefetch);
+
+       REG_SET(PREFETCH_SETTINGS_C, 0,
+                       VRATIO_PREFETCH_C, pipe_regs->dlg_regs.vratio_prefetch_c);
+
+       REG_SET_2(VBLANK_PARAMETERS_0, 0,
+               DST_Y_PER_VM_VBLANK, pipe_regs->dlg_regs.dst_y_per_vm_vblank,
+               DST_Y_PER_ROW_VBLANK, pipe_regs->dlg_regs.dst_y_per_row_vblank);
+
+       REG_SET_2(FLIP_PARAMETERS_0, 0,
+               DST_Y_PER_VM_FLIP, pipe_regs->dlg_regs.dst_y_per_vm_flip,
+               DST_Y_PER_ROW_FLIP, pipe_regs->dlg_regs.dst_y_per_row_flip);
 
+       REG_SET(VBLANK_PARAMETERS_3, 0,
+               REFCYC_PER_META_CHUNK_VBLANK_L, pipe_regs->dlg_regs.refcyc_per_meta_chunk_vblank_l);
+
+       REG_SET(VBLANK_PARAMETERS_4, 0,
+               REFCYC_PER_META_CHUNK_VBLANK_C, pipe_regs->dlg_regs.refcyc_per_meta_chunk_vblank_c);
+
+       REG_SET(FLIP_PARAMETERS_2, 0,
+               REFCYC_PER_META_CHUNK_FLIP_L, pipe_regs->dlg_regs.refcyc_per_meta_chunk_flip_l);
+
+       REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
+               REFCYC_PER_LINE_DELIVERY_PRE_L, pipe_regs->dlg_regs.refcyc_per_line_delivery_pre_l,
+               REFCYC_PER_LINE_DELIVERY_PRE_C, pipe_regs->dlg_regs.refcyc_per_line_delivery_pre_c);
+
+       REG_SET(DCN_SURF0_TTU_CNTL1, 0,
+               REFCYC_PER_REQ_DELIVERY_PRE,
+               pipe_regs->ttu_regs.refcyc_per_req_delivery_pre_l);
+       REG_SET(DCN_SURF1_TTU_CNTL1, 0,
+               REFCYC_PER_REQ_DELIVERY_PRE,
+               pipe_regs->ttu_regs.refcyc_per_req_delivery_pre_c);
+       REG_SET(DCN_CUR0_TTU_CNTL1, 0,
+               REFCYC_PER_REQ_DELIVERY_PRE, pipe_regs->ttu_regs.refcyc_per_req_delivery_pre_cur0);
+
+       REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
+               MIN_TTU_VBLANK, pipe_regs->ttu_regs.min_ttu_vblank,
+               QoS_LEVEL_FLIP, pipe_regs->ttu_regs.qos_level_flip);
+
+       REG_SET(DST_Y_DELTA_DRQ_LIMIT, 0,
+               DST_Y_DELTA_DRQ_LIMIT, pipe_regs->dlg_regs.dst_y_delta_drq_limit);
+}
 struct hubp_funcs dcn42_hubp_funcs = {
        .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
        .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
@@ -588,7 +637,7 @@ struct hubp_funcs dcn42_hubp_funcs = {
        .hubp_program_surface_config = hubp42_program_surface_config,
        .hubp_is_flip_pending = hubp2_is_flip_pending,
        .hubp_setup2 = hubp42_setup,
-       .hubp_setup_interdependent2 = hubp401_setup_interdependent,
+       .hubp_setup_interdependent2 = hubp42_setup_interdependent,
        .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings,
        .set_blank = hubp2_set_blank,
        .set_blank_regs = hubp2_set_blank_regs,

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h
index 27528f8..ba4a58c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h
@@ -97,4 +97,7 @@ void hubp42_setup(
                union dml2_global_sync_programming *pipe_global_sync,
                struct dc_crtc_timing *timing);
 
+void hubp42_setup_interdependent(
+               struct hubp *hubp,
+               struct dml2_dchub_per_pipe_register_set *pipe_regs);
 #endif /* __DC_HUBP_DCN42_H__ */