atl1c: show correct link speed on Mikrotik 10/25G NIC
authorGatis Peisenieks <gatis@mikrotik.com>
Thu, 13 May 2021 11:43:22 +0000 (14:43 +0300)
committerDavid S. Miller <davem@davemloft.net>
Thu, 13 May 2021 22:48:10 +0000 (15:48 -0700)
The new Mikrotik 10/25G NIC maintains compatibility with existing atl1c
driver. However it does have new features.

This defines some new register offsets, code for identifying the new type
of NIC and correct speed detection for the NIC.

Signed-off-by: Gatis Peisenieks <gatis@mikrotik.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/atheros/atl1c/atl1c.h
drivers/net/ethernet/atheros/atl1c/atl1c_hw.c
drivers/net/ethernet/atheros/atl1c/atl1c_hw.h
drivers/net/ethernet/atheros/atl1c/atl1c_main.c

index 28ae5c1..3fda7eb 100644 (file)
@@ -289,6 +289,7 @@ enum atl1c_nic_type {
        athr_l2c_b2,
        athr_l1d,
        athr_l1d_2,
+       athr_mt,
 };
 
 enum atl1c_trans_queue {
index 140358d..ddb9442 100644 (file)
@@ -648,6 +648,15 @@ int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex)
        int err;
        u16 phy_data;
 
+       if (hw->nic_type == athr_mt) {
+               u32 spd;
+
+               AT_READ_REG(hw, REG_MT_SPEED, &spd);
+               *speed = spd;
+               *duplex = FULL_DUPLEX;
+               return 0;
+       }
+
        /* Read   PHY Specific Status Register (17) */
        err = atl1c_read_phy_reg(hw, MII_GIGA_PSSR, &phy_data);
        if (err)
index ce1a123..73cbc04 100644 (file)
@@ -764,6 +764,13 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
 #define REG_DEBUG_DATA0                0x1900
 #define REG_DEBUG_DATA1                0x1904
 
+#define REG_MT_MAGIC                   0x1F00
+#define REG_MT_MODE                    0x1F04
+#define REG_MT_SPEED                   0x1F08
+#define REG_MT_VERSION                 0x1F0C
+
+#define MT_MAGIC                       0xaabb1234
+
 #define L1D_MPW_PHYID1                 0xD01C  /* V7 */
 #define L1D_MPW_PHYID2                 0xD01D  /* V1-V6 */
 #define L1D_MPW_PHYID3                 0xD01E  /* V8 */
index c6263cf..28c30d5 100644 (file)
@@ -644,6 +644,7 @@ static int atl1c_alloc_queues(struct atl1c_adapter *adapter)
 
 static void atl1c_set_mac_type(struct atl1c_hw *hw)
 {
+       u32 magic;
        switch (hw->device_id) {
        case PCI_DEVICE_ID_ATTANSIC_L2C:
                hw->nic_type = athr_l2c;
@@ -662,6 +663,9 @@ static void atl1c_set_mac_type(struct atl1c_hw *hw)
                break;
        case PCI_DEVICE_ID_ATHEROS_L1D_2_0:
                hw->nic_type = athr_l1d_2;
+               AT_READ_REG(hw, REG_MT_MAGIC, &magic);
+               if (magic == MT_MAGIC)
+                       hw->nic_type = athr_mt;
                break;
        default:
                break;