drm/i915/tgl+: Use the correct DP_TP_* register instances in MST encoders

MST encoders must use the master MST transcoder's DP_TP_STATUS and
DP_TP_CONTROL registers. Atm, during the HW readout of an MST encoder
connected to a slave transcoder we reset these register addresses in
intel_dp::regs.dp_tp_* to the slave transcoder's DP_TP_* register
addresses incorrectly; fix this.

One example where the above overwite happens is the encoder HW state
validation after enabling multiple streams; see
intel_dp_mst_enc_get_config(). After that during disabling any stream
we'll get a

'Timed out waiting for ACT sent when disabling'

error, due to reading from the incorrect DP_TP_STATUS register.

This change replaces
https://patchwork.freedesktop.org/patch/369577/?series=78193&rev=1
which just papered over the problem.

v2:
- Correct the failure scenario in the commit log. (José)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200616211146.23027-1-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ca7bb22..73d6cc2 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4193,11 +4193,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
        if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
                return;
 
-       if (INTEL_GEN(dev_priv) >= 12) {
-               intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(cpu_transcoder);
-               intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(cpu_transcoder);
-       }
-
        intel_dsc_get_config(encoder, pipe_config);
 
        temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
@@ -4299,6 +4294,16 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
                break;
        }
 
+       if (INTEL_GEN(dev_priv) >= 12) {
+               enum transcoder transcoder =
+                       intel_dp_mst_is_slave_trans(pipe_config) ?
+                       pipe_config->mst_master_transcoder :
+                       pipe_config->cpu_transcoder;
+
+               intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
+               intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
+       }
+
        pipe_config->has_audio =
                intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);