riscv: Introduce Zicbop instructions

The S-type instructions are first introduced and then used to define the
encoding of the Zicbop prefetching instructions.

Co-developed-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Guo Ren <guoren@kernel.org>
Tested-by: Andrea Parri <parri.andrea@gmail.com>
Link: https://lore.kernel.org/r/20250421142441.395849-2-alexghiti@rivosinc.com
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>

diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h
index 71060a2..02c92c1 100644 (file)
--- a/arch/riscv/include/asm/insn-def.h
+++ b/arch/riscv/include/asm/insn-def.h
@@ -18,6 +18,13 @@
 #define INSN_I_RD_SHIFT                         7
 #define INSN_I_OPCODE_SHIFT             0
 
+#define INSN_S_SIMM7_SHIFT             25
+#define INSN_S_RS2_SHIFT               20
+#define INSN_S_RS1_SHIFT               15
+#define INSN_S_FUNC3_SHIFT             12
+#define INSN_S_SIMM5_SHIFT              7
+#define INSN_S_OPCODE_SHIFT             0
+
 #ifdef __ASSEMBLY__
 
 #ifdef CONFIG_AS_HAS_INSN
@@ -30,6 +37,10 @@
        .insn   i \opcode, \func3, \rd, \rs1, \simm12
        .endm
 
+       .macro insn_s, opcode, func3, rs2, simm12, rs1
+       .insn   s \opcode, \func3, \rs2, \simm12(\rs1)
+       .endm
+
 #else
 
 #include <asm/gpr-num.h>
@@ -51,10 +62,20 @@
                 (\simm12 << INSN_I_SIMM12_SHIFT))
        .endm
 
+       .macro insn_s, opcode, func3, rs2, simm12, rs1
+       .4byte  ((\opcode << INSN_S_OPCODE_SHIFT) |             \
+                (\func3 << INSN_S_FUNC3_SHIFT) |               \
+                (.L__gpr_num_\rs2 << INSN_S_RS2_SHIFT) |       \
+                (.L__gpr_num_\rs1 << INSN_S_RS1_SHIFT) |       \
+                ((\simm12 & 0x1f) << INSN_S_SIMM5_SHIFT) |     \
+                (((\simm12 >> 5) & 0x7f) << INSN_S_SIMM7_SHIFT))
+       .endm
+
 #endif
 
 #define __INSN_R(...)  insn_r __VA_ARGS__
 #define __INSN_I(...)  insn_i __VA_ARGS__
+#define __INSN_S(...)  insn_s __VA_ARGS__
 
 #else /* ! __ASSEMBLY__ */
 
@@ -66,6 +87,9 @@
 #define __INSN_I(opcode, func3, rd, rs1, simm12)       \
        ".insn  i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n"
 
+#define __INSN_S(opcode, func3, rs2, simm12, rs1)      \
+       ".insn  s " opcode ", " func3 ", " rs2 ", " simm12 "(" rs1 ")\n"
+
 #else
 
 #include <linux/stringify.h>
@@ -92,12 +116,26 @@
 "               (\\simm12 << " __stringify(INSN_I_SIMM12_SHIFT) "))\n" \
 "      .endm\n"
 
+#define DEFINE_INSN_S                                                  \
+       __DEFINE_ASM_GPR_NUMS                                           \
+"      .macro insn_s, opcode, func3, rs2, simm12, rs1\n"               \
+"      .4byte  ((\\opcode << " __stringify(INSN_S_OPCODE_SHIFT) ") |"  \
+"               (\\func3 << " __stringify(INSN_S_FUNC3_SHIFT) ") |"    \
+"               (.L__gpr_num_\\rs2 << " __stringify(INSN_S_RS2_SHIFT) ") |" \
+"               (.L__gpr_num_\\rs1 << " __stringify(INSN_S_RS1_SHIFT) ") |" \
+"               ((\\simm12 & 0x1f) << " __stringify(INSN_S_SIMM5_SHIFT) ") |" \
+"               (((\\simm12 >> 5) & 0x7f) << " __stringify(INSN_S_SIMM7_SHIFT) "))\n" \
+"      .endm\n"
+
 #define UNDEFINE_INSN_R                                                        \
 "      .purgem insn_r\n"
 
 #define UNDEFINE_INSN_I                                                        \
 "      .purgem insn_i\n"
 
+#define UNDEFINE_INSN_S                                                        \
+"      .purgem insn_s\n"
+
 #define __INSN_R(opcode, func3, func7, rd, rs1, rs2)                   \
        DEFINE_INSN_R                                                   \
        "insn_r " opcode ", " func3 ", " func7 ", " rd ", " rs1 ", " rs2 "\n" \
@@ -108,6 +146,11 @@
        "insn_i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n" \
        UNDEFINE_INSN_I
 
+#define __INSN_S(opcode, func3, rs2, simm12, rs1)                      \
+       DEFINE_INSN_S                                                   \
+       "insn_s " opcode ", " func3 ", " rs2 ", " simm12 ", " rs1 "\n"  \
+       UNDEFINE_INSN_S
+
 #endif
 
 #endif /* ! __ASSEMBLY__ */
@@ -120,6 +163,10 @@
        __INSN_I(RV_##opcode, RV_##func3, RV_##rd,              \
                 RV_##rs1, RV_##simm12)
 
+#define INSN_S(opcode, func3, rs2, simm12, rs1)                        \
+       __INSN_S(RV_##opcode, RV_##func3, RV_##rs2,             \
+                RV_##simm12, RV_##rs1)
+
 #define RV_OPCODE(v)           __ASM_STR(v)
 #define RV_FUNC3(v)            __ASM_STR(v)
 #define RV_FUNC7(v)            __ASM_STR(v)
@@ -133,6 +180,7 @@
 #define RV___RS2(v)            __RV_REG(v)
 
 #define RV_OPCODE_MISC_MEM     RV_OPCODE(15)
+#define RV_OPCODE_OP_IMM       RV_OPCODE(19)
 #define RV_OPCODE_SYSTEM       RV_OPCODE(115)
 
 #define HFENCE_VVMA(vaddr, asid)                               \
@@ -196,6 +244,18 @@
        INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0),              \
               RS1(base), SIMM12(4))
 
+#define PREFETCH_I(base, offset)                               \
+       INSN_S(OPCODE_OP_IMM, FUNC3(6), __RS2(0),               \
+              SIMM12((offset) & 0xfe0), RS1(base))
+
+#define PREFETCH_R(base, offset)                               \
+       INSN_S(OPCODE_OP_IMM, FUNC3(6), __RS2(1),               \
+              SIMM12((offset) & 0xfe0), RS1(base))
+
+#define PREFETCH_W(base, offset)                               \
+       INSN_S(OPCODE_OP_IMM, FUNC3(6), __RS2(3),               \
+              SIMM12((offset) & 0xfe0), RS1(base))
+
 #define RISCV_PAUSE    ".4byte 0x100000f"
 #define ZAWRS_WRS_NTO  ".4byte 0x00d00073"
 #define ZAWRS_WRS_STO  ".4byte 0x01d00073"