core_dc->hwss.init_hw(core_dc);
full_pipe_count = core_dc->res_pool->pipe_count;
- if (core_dc->res_pool->underlay_pipe_index >= 0)
+ if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
full_pipe_count--;
core_dc->public.caps.max_streams = min(
full_pipe_count,
pool->base.res_cap = &res_cap;
pool->base.funcs = &dce100_res_pool_funcs;
- pool->base.underlay_pipe_index = -1;
+ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
bp = ctx->dc_bios;
/*************************************************
* Resource + asic cap harcoding *
*************************************************/
- pool->base.underlay_pipe_index = -1;
+ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
pool->base.pipe_count = res_cap.num_timing_generator;
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 40;
/*************************************************
* Resource + asic cap harcoding *
*************************************************/
- pool->base.underlay_pipe_index = -1;
+ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 100;
/*************************************************
* Resource + asic cap harcoding *
*************************************************/
- pool->base.underlay_pipe_index = -1;
+ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
pool->base.pipe_count = res_cap.num_timing_generator;
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 40;
bool hdmi_audio_native;
};
+#define NO_UNDERLAY_PIPE -1
+
struct resource_pool {
struct mem_input *mis[MAX_PIPES];
struct input_pixel_processor *ipps[MAX_PIPES];