arm64: dts: renesas: r8a779g0: Add L3 cache controller

Describe the cache configuration for the first Cortex-A76 CPU core on
the Renesas R-Car V4H (R8A779G0) SoC.

Extracted from a larger patch in the BSP by Takeshi Kihara.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/dfd743b32198295afb78bc0ac337ef283fa3879a.1668429870.git.geert+renesas@glider.be

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index 0ea48fa..ef75e26 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -23,6 +23,14 @@
                        reg = <0>;
                        device_type = "cpu";
                        power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
+                       next-level-cache = <&L3_CA76_0>;
+               };
+
+               L3_CA76_0: cache-controller-0 {
+                       compatible = "cache";
+                       power-domains = <&sysc R8A779G0_PD_A2E0D0>;
+                       cache-unified;
+                       cache-level = <3>;
                };
        };