ARM: dts: rockchip: Assign the proper GPIO clocks for rv1108
authorOtavio Salvador <otavio@ossystems.com.br>
Mon, 26 Nov 2018 17:35:04 +0000 (15:35 -0200)
committerHeiko Stuebner <heiko@sntech.de>
Tue, 27 Nov 2018 00:07:32 +0000 (01:07 +0100)
It is not correct to assign the 24MHz clock oscillator to the GPIO
ports.

Fix it by assigning the proper GPIO clocks instead.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Tested-by: Fabio Berton <fabio.berton@ossystems.com.br>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm/boot/dts/rv1108.dtsi

index 611f2fe..300de8e 100644 (file)
                        compatible = "rockchip,gpio-bank";
                        reg = <0x20030000 0x100>;
                        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&xin24m>;
+                       clocks = <&cru PCLK_GPIO0_PMU>;
 
                        gpio-controller;
                        #gpio-cells = <2>;
                        compatible = "rockchip,gpio-bank";
                        reg = <0x10310000 0x100>;
                        interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&xin24m>;
+                       clocks = <&cru PCLK_GPIO1>;
 
                        gpio-controller;
                        #gpio-cells = <2>;
                        compatible = "rockchip,gpio-bank";
                        reg = <0x10320000 0x100>;
                        interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&xin24m>;
+                       clocks = <&cru PCLK_GPIO2>;
 
                        gpio-controller;
                        #gpio-cells = <2>;
                        compatible = "rockchip,gpio-bank";
                        reg = <0x10330000 0x100>;
                        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&xin24m>;
+                       clocks = <&cru PCLK_GPIO3>;
 
                        gpio-controller;
                        #gpio-cells = <2>;