drm/xe/execlist: Convert register access to use xe_mmio

Stop using GT pointers for register access.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240910234719.3335472-78-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
index 6a59165..f3b71fe 100644 (file)
--- a/drivers/gpu/drm/xe/xe_execlist.c
+++ b/drivers/gpu/drm/xe/xe_execlist.c
@@ -44,6 +44,7 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
                        u32 ctx_id)
 {
        struct xe_gt *gt = hwe->gt;
+       struct xe_mmio *mmio = &gt->mmio;
        struct xe_device *xe = gt_to_xe(gt);
        u64 lrc_desc;
 
@@ -58,7 +59,7 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
        }
 
        if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
-               xe_mmio_write32(hwe->gt, RCU_MODE,
+               xe_mmio_write32(mmio, RCU_MODE,
                                _MASKED_BIT_ENABLE(RCU_MODE_CCS_ENABLE));
 
        xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail);
@@ -76,17 +77,17 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
         */
        wmb();
 
-       xe_mmio_write32(gt, RING_HWS_PGA(hwe->mmio_base),
+       xe_mmio_write32(mmio, RING_HWS_PGA(hwe->mmio_base),
                        xe_bo_ggtt_addr(hwe->hwsp));
-       xe_mmio_read32(gt, RING_HWS_PGA(hwe->mmio_base));
-       xe_mmio_write32(gt, RING_MODE(hwe->mmio_base),
+       xe_mmio_read32(mmio, RING_HWS_PGA(hwe->mmio_base));
+       xe_mmio_write32(mmio, RING_MODE(hwe->mmio_base),
                        _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE));
 
-       xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base),
+       xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base),
                        lower_32_bits(lrc_desc));
-       xe_mmio_write32(gt, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base),
+       xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_HI(hwe->mmio_base),
                        upper_32_bits(lrc_desc));
-       xe_mmio_write32(gt, RING_EXECLIST_CONTROL(hwe->mmio_base),
+       xe_mmio_write32(mmio, RING_EXECLIST_CONTROL(hwe->mmio_base),
                        EL_CTRL_LOAD);
 }
 
@@ -168,8 +169,8 @@ static u64 read_execlist_status(struct xe_hw_engine *hwe)
        struct xe_gt *gt = hwe->gt;
        u32 hi, lo;
 
-       lo = xe_mmio_read32(gt, RING_EXECLIST_STATUS_LO(hwe->mmio_base));
-       hi = xe_mmio_read32(gt, RING_EXECLIST_STATUS_HI(hwe->mmio_base));
+       lo = xe_mmio_read32(&gt->mmio, RING_EXECLIST_STATUS_LO(hwe->mmio_base));
+       hi = xe_mmio_read32(&gt->mmio, RING_EXECLIST_STATUS_HI(hwe->mmio_base));
 
        return lo | (u64)hi << 32;
 }