riscv: dts: starfive: Add JH7100 CPU topology

Add cpu-map binding to inform the kernel about the hardware topology
of the CPU cores.

Before this change, lstopo would report 1 core with 2 threads:
Machine (7231MB total)
  Package L#0
    NUMANode L#0 (P#0 7231MB)
    L2 L#0 (2048KB) + Core L#0
      L1d L#0 (32KB) + L1i L#0 (32KB) + PU L#0 (P#0)
      L1d L#1 (32KB) + L1i L#1 (32KB) + PU L#1 (P#1)

After this change, it correctly identifies two cores:
Machine (7231MB total)
  Package L#0
    NUMANode L#0 (P#0 7231MB)
    L2 L#0 (2048KB)
      L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0)
      L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1)

Signed-off-by: Jonas Hahnfeld <hahnjo@hahnjo.de>
Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220705190435.1790466-2-mail@conchuod.ie
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 69f22f9..c617a61 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -17,7 +17,7 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
-               cpu@0 {
+               U74_0: cpu@0 {
                        compatible = "sifive,u74-mc", "riscv";
                        reg = <0>;
                        d-cache-block-size = <64>;
@@ -42,7 +42,7 @@
                        };
                };
 
-               cpu@1 {
+               U74_1: cpu@1 {
                        compatible = "sifive,u74-mc", "riscv";
                        reg = <1>;
                        d-cache-block-size = <64>;
@@ -66,6 +66,18 @@
                                #interrupt-cells = <1>;
                        };
                };
+
+               cpu-map {
+                       cluster0 {
+                               core0 {
+                                       cpu = <&U74_0>;
+                               };
+
+                               core1 {
+                                       cpu = <&U74_1>;
+                               };
+                       };
+               };
        };
 
        osc_sys: osc_sys {