ARM: dts: exynos: Add S5M8767 clocks for RTC in Exynos4412 Origen

Add node for clock controller of Samsung S5M8767 PMIC.  This provides
the 32768 Hz clock required by S3C RTC.  Except making the S3C RTC
working, this also fixes dtbs_check warnings:

  arch/arm/boot/dts/exynos4412-origen.dt.yaml: rtc@10070000: clocks: [[7, 346]] is too short
  arch/arm/boot/dts/exynos4412-origen.dt.yaml: rtc@10070000: clock-names: ['rtc'] is too short

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200830135200.24304-25-krzk@kernel.org

diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 8b11ad3..4c52ca6 100644 (file)
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -11,6 +11,7 @@
 
 /dts-v1/;
 #include "exynos4412.dtsi"
+#include <dt-bindings/clock/samsung,s2mps11.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include "exynos-mfc-reserved-memory.dtsi"
@@ -129,6 +130,13 @@
                                                 <1200000>, <1200000>,
                                                 <1200000>, <1200000>;
 
+               s5m8767_osc: clocks {
+                       compatible = "samsung,s5m8767-clk";
+                       #clock-cells = <1>;
+                       clock-output-names = "s5m8767_ap", "s5m8767_cp",
+                                            "s5m8767_bt";
+               };
+
                regulators {
                        ldo1_reg: LDO1 {
                                regulator-name = "VDD_ALIVE";
@@ -499,6 +507,8 @@
 
 &rtc {
        status = "okay";
+       clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>;
+       clock-names = "rtc", "rtc_src";
 };
 
 &sdhci_2 {