#define SST_CLKCTL             0x78
 #define SST_CSR2               0x80
 #define SST_LTRC               0xE0
-#define SST_HDMC               0xE8
+#define SST_HMDC               0xE8
 
 #define SST_SHIM_BEGIN         SST_CSR
 #define SST_SHIM_END           SST_HDMC
 /* LTRC */
 #define SST_LTRC_VAL(x)                (x << 0)
 
-/* HDMC */
-#define SST_HDMC_HDDA0(x)      (x << 0)
-#define SST_HDMC_HDDA1(x)      (x << 7)
+/* HMDC */
+#define SST_HMDC_HDDA0(x)      (x << 0)
+#define SST_HMDC_HDDA1(x)      (x << 7)
 
 
 /* SST Vendor Defined Registers and bits */
 
                SST_CSR2_SDFD_SSP1);
 
        /* enable DMA engine 0,1 all channels to access host memory */
-       sst_dsp_shim_update_bits_unlocked(sst, SST_HDMC,
-               SST_HDMC_HDDA1(0xff)  | SST_HDMC_HDDA0(0xff),
-               SST_HDMC_HDDA1(0xff) | SST_HDMC_HDDA0(0xff));
+       sst_dsp_shim_update_bits_unlocked(sst, SST_HMDC,
+               SST_HMDC_HDDA1(0xff) | SST_HMDC_HDDA0(0xff),
+               SST_HMDC_HDDA1(0xff) | SST_HMDC_HDDA0(0xff));
 
        /* disable all clock gating */
        writel(0x0, sst->addr.pci_cfg + SST_VDRTCTL2);