Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

Pull kvm updates from Paolo Bonzini:
 "ARM:

   - Nested virtualization support for VGICv3, giving the nested
     hypervisor control of the VGIC hardware when running an L2 VM

   - Removal of 'late' nested virtualization feature register masking,
     making the supported feature set directly visible to userspace

   - Support for emulating FEAT_PMUv3 on Apple silicon, taking advantage
     of an IMPLEMENTATION DEFINED trap that covers all PMUv3 registers

   - Paravirtual interface for discovering the set of CPU
     implementations where a VM may run, addressing a longstanding issue
     of guest CPU errata awareness in big-little systems and
     cross-implementation VM migration

   - Userspace control of the registers responsible for identifying a
     particular CPU implementation (MIDR_EL1, REVIDR_EL1, AIDR_EL1),
     allowing VMs to be migrated cross-implementation

   - pKVM updates, including support for tracking stage-2 page table
     allocations in the protected hypervisor in the 'SecPageTable' stat

   - Fixes to vPMU, ensuring that userspace updates to the vPMU after
     KVM_RUN are reflected into the backing perf events

  LoongArch:

   - Remove unnecessary header include path

   - Assume constant PGD during VM context switch

   - Add perf events support for guest VM

  RISC-V:

   - Disable the kernel perf counter during configure

   - KVM selftests improvements for PMU

   - Fix warning at the time of KVM module removal

  x86:

   - Add support for aging of SPTEs without holding mmu_lock.

     Not taking mmu_lock allows multiple aging actions to run in
     parallel, and more importantly avoids stalling vCPUs. This includes
     an implementation of per-rmap-entry locking; aging the gfn is done
     with only a per-rmap single-bin spinlock taken, whereas locking an
     rmap for write requires taking both the per-rmap spinlock and the
     mmu_lock.

     Note that this decreases slightly the accuracy of accessed-page
     information, because changes to the SPTE outside aging might not
     use atomic operations even if they could race against a clear of
     the Accessed bit.

     This is deliberate because KVM and mm/ tolerate false
     positives/negatives for accessed information, and testing has shown
     that reducing the latency of aging is far more beneficial to
     overall system performance than providing "perfect" young/old
     information.

   - Defer runtime CPUID updates until KVM emulates a CPUID instruction,
     to coalesce updates when multiple pieces of vCPU state are
     changing, e.g. as part of a nested transition

   - Fix a variety of nested emulation bugs, and add VMX support for
     synthesizing nested VM-Exit on interception (instead of injecting
     #UD into L2)

   - Drop "support" for async page faults for protected guests that do
     not set SEND_ALWAYS (i.e. that only want async page faults at CPL3)

   - Bring a bit of sanity to x86's VM teardown code, which has
     accumulated a lot of cruft over the years. Particularly, destroy
     vCPUs before the MMU, despite the latter being a VM-wide operation

   - Add common secure TSC infrastructure for use within SNP and in the
     future TDX

   - Block KVM_CAP_SYNC_REGS if guest state is protected. It does not
     make sense to use the capability if the relevant registers are not
     available for reading or writing

   - Don't take kvm->lock when iterating over vCPUs in the suspend
     notifier to fix a largely theoretical deadlock

   - Use the vCPU's actual Xen PV clock information when starting the
     Xen timer, as the cached state in arch.hv_clock can be stale/bogus

   - Fix a bug where KVM could bleed PVCLOCK_GUEST_STOPPED across
     different PV clocks; restrict PVCLOCK_GUEST_STOPPED to kvmclock, as
     KVM's suspend notifier only accounts for kvmclock, and there's no
     evidence that the flag is actually supported by Xen guests

   - Clean up the per-vCPU "cache" of its reference pvclock, and instead
     only track the vCPU's TSC scaling (multipler+shift) metadata (which
     is moderately expensive to compute, and rarely changes for modern
     setups)

   - Don't write to the Xen hypercall page on MSR writes that are
     initiated by the host (userspace or KVM) to fix a class of bugs
     where KVM can write to guest memory at unexpected times, e.g.
     during vCPU creation if userspace has set the Xen hypercall MSR
     index to collide with an MSR that KVM emulates

   - Restrict the Xen hypercall MSR index to the unofficial synthetic
     range to reduce the set of possible collisions with MSRs that are
     emulated by KVM (collisions can still happen as KVM emulates
     Hyper-V MSRs, which also reside in the synthetic range)

   - Clean up and optimize KVM's handling of Xen MSR writes and
     xen_hvm_config

   - Update Xen TSC leaves during CPUID emulation instead of modifying
     the CPUID entries when updating PV clocks; there is no guarantee PV
     clocks will be updated between TSC frequency changes and CPUID
     emulation, and guest reads of the TSC leaves should be rare, i.e.
     are not a hot path

  x86 (Intel):

   - Fix a bug where KVM unnecessarily reads XFD_ERR from hardware and
     thus modifies the vCPU's XFD_ERR on a #NM due to CR0.TS=1

   - Pass XFD_ERR as the payload when injecting #NM, as a preparatory
     step for upcoming FRED virtualization support

   - Decouple the EPT entry RWX protection bit macros from the EPT
     Violation bits, both as a general cleanup and in anticipation of
     adding support for emulating Mode-Based Execution Control (MBEC)

   - Reject KVM_RUN if userspace manages to gain control and stuff
     invalid guest state while KVM is in the middle of emulating nested
     VM-Enter

   - Add a macro to handle KVM's sanity checks on entry/exit VMCS
     control pairs in anticipation of adding sanity checks for secondary
     exit controls (the primary field is out of bits)

  x86 (AMD):

   - Ensure the PSP driver is initialized when both the PSP and KVM
     modules are built-in (the initcall framework doesn't handle
     dependencies)

   - Use long-term pins when registering encrypted memory regions, so
     that the pages are migrated out of MIGRATE_CMA/ZONE_MOVABLE and
     don't lead to excessive fragmentation

   - Add macros and helpers for setting GHCB return/error codes

   - Add support for Idle HLT interception, which elides interception if
     the vCPU has a pending, unmasked virtual IRQ when HLT is executed

   - Fix a bug in INVPCID emulation where KVM fails to check for a
     non-canonical address

   - Don't attempt VMRUN for SEV-ES+ guests if the vCPU's VMSA is
     invalid, e.g. because the vCPU was "destroyed" via SNP's AP
     Creation hypercall

   - Reject SNP AP Creation if the requested SEV features for the vCPU
     don't match the VM's configured set of features

  Selftests:

   - Fix again the Intel PMU counters test; add a data load and do
     CLFLUSH{OPT} on the data instead of executing code. The theory is
     that modern Intel CPUs have learned new code prefetching tricks
     that bypass the PMU counters

   - Fix a flaw in the Intel PMU counters test where it asserts that an
     event is counting correctly without actually knowing what the event
     counts on the underlying hardware

   - Fix a variety of flaws, bugs, and false failures/passes
     dirty_log_test, and improve its coverage by collecting all dirty
     entries on each iteration

   - Fix a few minor bugs related to handling of stats FDs

   - Add infrastructure to make vCPU and VM stats FDs available to tests
     by default (open the FDs during VM/vCPU creation)

   - Relax an assertion on the number of HLT exits in the xAPIC IPI test
     when running on a CPU that supports AMD's Idle HLT (which elides
     interception of HLT if a virtual IRQ is pending and unmasked)"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (216 commits)
  RISC-V: KVM: Optimize comments in kvm_riscv_vcpu_isa_disable_allowed
  RISC-V: KVM: Teardown riscv specific bits after kvm_exit
  LoongArch: KVM: Register perf callbacks for guest
  LoongArch: KVM: Implement arch-specific functions for guest perf
  LoongArch: KVM: Add stub for kvm_arch_vcpu_preempted_in_kernel()
  LoongArch: KVM: Remove PGD saving during VM context switch
  LoongArch: KVM: Remove unnecessary header include path
  KVM: arm64: Tear down vGIC on failed vCPU creation
  KVM: arm64: PMU: Reload when resetting
  KVM: arm64: PMU: Reload when user modifies registers
  KVM: arm64: PMU: Fix SET_ONE_REG for vPMC regs
  KVM: arm64: PMU: Assume PMU presence in pmu-emul.c
  KVM: arm64: PMU: Set raw values from user to PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR}
  KVM: arm64: Create each pKVM hyp vcpu after its corresponding host vcpu
  KVM: arm64: Factor out pKVM hyp vcpu creation to separate function
  KVM: arm64: Initialize HCRX_EL2 traps in pKVM
  KVM: arm64: Factor out setting HCRX_EL2 traps into separate function
  KVM: x86: block KVM_CAP_SYNC_REGS if guest state is protected
  KVM: x86: Add infrastructure for secure TSC
  KVM: x86: Push down setting vcpu.arch.user_set_tsc
  ...

diff --cc arch/arm64/include/asm/cputype.h
Simple merge

diff --cc arch/arm64/include/asm/sysreg.h
Simple merge

diff --cc arch/arm64/kernel/proton-pack.c
index 0f51fd1,a573fa4..d5d11fd
--- 1/arch/arm64/kernel/proton-pack.c
--- 2/arch/arm64/kernel/proton-pack.c
+++ b/arch/arm64/kernel/proton-pack.c
@@@ -845,86 -845,52 +845,86 @@@ static unsigned long system_bhb_mitigat
   * This must be called with SCOPE_LOCAL_CPU for each type of CPU, before any
   * SCOPE_SYSTEM call will give the right answer.
   */
 -u8 spectre_bhb_loop_affected(int scope)
 +static bool is_spectre_bhb_safe(int scope)
 +{
 +      static const struct midr_range spectre_bhb_safe_list[] = {
 +              MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
 +              MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 +              MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 +              MIDR_ALL_VERSIONS(MIDR_CORTEX_A510),
 +              MIDR_ALL_VERSIONS(MIDR_CORTEX_A520),
 +              MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
 +              MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
 +              MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
 +              MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
 +              {},
 +      };
 +      static bool all_safe = true;
 +
 +      if (scope != SCOPE_LOCAL_CPU)
 +              return all_safe;
 +
-       if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_safe_list))
++      if (is_midr_in_range_list(spectre_bhb_safe_list))
 +              return true;
 +
 +      all_safe = false;
 +
 +      return false;
 +}
 +
 +static u8 spectre_bhb_loop_affected(void)
  {
        u8 k = 0;
 -      static u8 max_bhb_k;
 -
 -      if (scope == SCOPE_LOCAL_CPU) {
 -              static const struct midr_range spectre_bhb_k32_list[] = {
 -                      MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
 -                      MIDR_ALL_VERSIONS(MIDR_CORTEX_A78AE),
 -                      MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
 -                      MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
 -                      MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
 -                      MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
 -                      MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
 -                      MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
 -                      {},
 -              };
 -              static const struct midr_range spectre_bhb_k24_list[] = {
 -                      MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
 -                      MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
 -                      MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
 -                      {},
 -              };
 -              static const struct midr_range spectre_bhb_k11_list[] = {
 -                      MIDR_ALL_VERSIONS(MIDR_AMPERE1),
 -                      {},
 -              };
 -              static const struct midr_range spectre_bhb_k8_list[] = {
 -                      MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 -                      MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 -                      {},
 -              };
 -
 -              if (is_midr_in_range_list(spectre_bhb_k32_list))
 -                      k = 32;
 -              else if (is_midr_in_range_list(spectre_bhb_k24_list))
 -                      k = 24;
 -              else if (is_midr_in_range_list(spectre_bhb_k11_list))
 -                      k = 11;
 -              else if (is_midr_in_range_list(spectre_bhb_k8_list))
 -                      k =  8;
 -
 -              max_bhb_k = max(max_bhb_k, k);
 -      } else {
 -              k = max_bhb_k;
 -      }
 +
 +      static const struct midr_range spectre_bhb_k132_list[] = {
 +              MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
 +              MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
 +      };
 +      static const struct midr_range spectre_bhb_k38_list[] = {
 +              MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
 +              MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
 +      };
 +      static const struct midr_range spectre_bhb_k32_list[] = {
 +              MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),
 +              MIDR_ALL_VERSIONS(MIDR_CORTEX_A78AE),
 +              MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),
 +              MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),
 +              MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
 +              MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
 +              MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
 +              MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
 +              {},
 +      };
 +      static const struct midr_range spectre_bhb_k24_list[] = {
 +              MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),
 +              MIDR_ALL_VERSIONS(MIDR_CORTEX_A76AE),
 +              MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),
 +              MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
 +              MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_GOLD),
 +              {},
 +      };
 +      static const struct midr_range spectre_bhb_k11_list[] = {
 +              MIDR_ALL_VERSIONS(MIDR_AMPERE1),
 +              {},
 +      };
 +      static const struct midr_range spectre_bhb_k8_list[] = {
 +              MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 +              MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 +              {},
 +      };
 +
-       if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k132_list))
++      if (is_midr_in_range_list(spectre_bhb_k132_list))
 +              k = 132;
-       else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k38_list))
++      else if (is_midr_in_range_list(spectre_bhb_k38_list))
 +              k = 38;
-       else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k32_list))
++      else if (is_midr_in_range_list(spectre_bhb_k32_list))
 +              k = 32;
-       else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k24_list))
++      else if (is_midr_in_range_list(spectre_bhb_k24_list))
 +              k = 24;
-       else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k11_list))
++      else if (is_midr_in_range_list(spectre_bhb_k11_list))
 +              k = 11;
-       else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k8_list))
++      else if (is_midr_in_range_list(spectre_bhb_k8_list))
 +              k =  8;
  
        return k;
  }

diff --cc arch/arm64/tools/sysreg
Simple merge

diff --cc arch/loongarch/kernel/asm-offsets.c
Simple merge

diff --cc arch/loongarch/kvm/vcpu.c
index dbf5d7a,552cde7..8e427b3
--- 1/arch/loongarch/kvm/vcpu.c
--- 2/arch/loongarch/kvm/vcpu.c
+++ b/arch/loongarch/kvm/vcpu.c
@@@ -1459,9 -1487,18 +1487,18 @@@ int kvm_arch_vcpu_create(struct kvm_vcp
        vcpu->arch.vpid = 0;
        vcpu->arch.flush_gpa = INVALID_GPA;
  
 -      hrtimer_init(&vcpu->arch.swtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS_PINNED_HARD);
 -      vcpu->arch.swtimer.function = kvm_swtimer_wakeup;
 +      hrtimer_setup(&vcpu->arch.swtimer, kvm_swtimer_wakeup, CLOCK_MONOTONIC,
 +                    HRTIMER_MODE_ABS_PINNED_HARD);
  
+       /* Get GPA (=HVA) of PGD for kvm hypervisor */
+       vcpu->arch.kvm_pgd = __pa(vcpu->kvm->arch.pgd);
+ 
+       /*
+        * Get PGD for primary mmu, virtual address is used since there is
+        * memory access after loading from CSR_PGD in tlb exception fast path.
+        */
+       vcpu->arch.host_pgd = (unsigned long)vcpu->kvm->mm->pgd;
+ 
        vcpu->arch.handle_exit = kvm_handle_exit;
        vcpu->arch.guest_eentry = (unsigned long)kvm_loongarch_ops->exc_entry;
        vcpu->arch.csr = kzalloc(sizeof(struct loongarch_csrs), GFP_KERNEL);

diff --cc arch/x86/include/asm/cpufeatures.h
Simple merge

diff --cc arch/x86/kvm/lapic.c
Simple merge

diff --cc arch/x86/kvm/svm/svm.c
Simple merge

diff --cc arch/x86/kvm/vmx/nested.c
Simple merge

diff --cc arch/x86/kvm/vmx/vmx.c
Simple merge

diff --cc arch/x86/kvm/xen.c
Simple merge

diff --cc drivers/perf/apple_m1_cpu_pmu.c
Simple merge

diff --cc include/linux/perf/arm_pmu.h
index c70d528,7ce6dea..6dc5e0c
--- 1/include/linux/perf/arm_pmu.h
--- 2/include/linux/perf/arm_pmu.h
+++ b/include/linux/perf/arm_pmu.h
@@@ -99,8 -100,16 +99,12 @@@ struct arm_pmu 
        void            (*stop)(struct arm_pmu *);
        void            (*reset)(void *);
        int             (*map_event)(struct perf_event *event);
+       /*
+        * Called by KVM to map the PMUv3 event space onto non-PMUv3 hardware.
+        */
+       int             (*map_pmuv3_event)(unsigned int eventsel);
        DECLARE_BITMAP(cntr_mask, ARMPMU_MAX_HWEVENTS);
        bool            secure_access; /* 32-bit ARM only */
 -#define ARMV8_PMUV3_MAX_COMMON_EVENTS         0x40
 -      DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
 -#define ARMV8_PMUV3_EXT_COMMON_EVENT_BASE     0x4000
 -      DECLARE_BITMAP(pmceid_ext_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
        struct platform_device  *plat_device;
        struct pmu_hw_events    __percpu *hw_events;
        struct hlist_node       node;

diff --cc virt/kvm/kvm_main.c
Simple merge