arm64: dts: qcom: sm8450: Add missing RPMhPD OPP levels
authorKonrad Dybcio <konrad.dybcio@linaro.org>
Tue, 16 May 2023 00:53:06 +0000 (02:53 +0200)
committerBjorn Andersson <andersson@kernel.org>
Thu, 25 May 2023 04:50:46 +0000 (21:50 -0700)
We need more granularity for things like the GPU. Add the missing levels.

This unfortunately requires some re-indexing, resulting in an ugly diff.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230516005306.952821-1-konrad.dybcio@linaro.org
arch/arm64/boot/dts/qcom/sm8450.dtsi

index 174a23b..f853032 100644 (file)
                                                opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
                                        };
 
-                                       rpmhpd_opp_svs: opp5 {
+                                       rpmhpd_opp_low_svs_l1: opp5 {
+                                               opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
+                                       };
+
+                                       rpmhpd_opp_svs: opp6 {
                                                opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
                                        };
 
-                                       rpmhpd_opp_svs_l1: opp6 {
+                                       rpmhpd_opp_svs_l0: opp7 {
+                                               opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+                                       };
+
+                                       rpmhpd_opp_svs_l1: opp8 {
                                                opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
                                        };
 
-                                       rpmhpd_opp_nom: opp7 {
+                                       rpmhpd_opp_svs_l2: opp9 {
+                                               opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+                                       };
+
+                                       rpmhpd_opp_nom: opp10 {
                                                opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
                                        };
 
-                                       rpmhpd_opp_nom_l1: opp8 {
+                                       rpmhpd_opp_nom_l1: opp11 {
                                                opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
                                        };
 
-                                       rpmhpd_opp_nom_l2: opp9 {
+                                       rpmhpd_opp_nom_l2: opp12 {
                                                opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
                                        };
 
-                                       rpmhpd_opp_turbo: opp10 {
+                                       rpmhpd_opp_turbo: opp13 {
                                                opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
                                        };
 
-                                       rpmhpd_opp_turbo_l1: opp11 {
+                                       rpmhpd_opp_turbo_l1: opp14 {
                                                opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
                                        };
                                };