dt-bindings: gpu: add bindings for the ARM Mali Bifrost GPU
authorNeil Armstrong <narmstrong@baylibre.com>
Mon, 1 Apr 2019 08:09:49 +0000 (10:09 +0200)
committerNeil Armstrong <narmstrong@baylibre.com>
Tue, 9 Apr 2019 08:18:31 +0000 (10:18 +0200)
Add the bindings for the Bifrost family of ARM Mali GPUs.

The Bifrost GPU architecture is similar to the Midgard family,
but with a different Shader Core & Execution Engine structures.

Bindings are based on the Midgard family bindings, but the inner
architectural changes makes it a separate family needing separate
bindings.

The Bifrost GPUs are present in a number of recent SoCs, like the
Amlogic G12A Family, and many other vendors.
The Amlogic vendor specific compatible is added to handle the
specific IP integration differences and dependencies.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
[narmstrong: fixed small typo in compatible description]
Link: https://patchwork.freedesktop.org/patch/msgid/20190401080949.14550-1-narmstrong@baylibre.com
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.txt
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index 0000000..b8be9db
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+ARM Mali Bifrost GPU
+====================
+
+Required properties:
+
+- compatible :
+  * Since Mali Bifrost GPU model/revision is fully discoverable by reading
+    some determined registers, must contain the following:
+    + "arm,mali-bifrost"
+  * which must be preceded by one of the following vendor specifics:
+    + "amlogic,meson-g12a-mali"
+
+- reg : Physical base address of the device and length of the register area.
+
+- interrupts : Contains the three IRQ lines required by Mali Bifrost devices,
+  in the following defined order.
+
+- interrupt-names : Contains the names of IRQ resources in this exact defined
+  order: "job", "mmu", "gpu".
+
+Optional properties:
+
+- clocks : Phandle to clock for the Mali Bifrost device.
+
+- mali-supply : Phandle to regulator for the Mali device. Refer to
+  Documentation/devicetree/bindings/regulator/regulator.txt for details.
+
+- operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt
+  for details.
+
+- resets : Phandle of the GPU reset line.
+
+Vendor-specific bindings
+------------------------
+
+The Mali GPU is integrated very differently from one SoC to
+another. In order to accommodate those differences, you have the option
+to specify one more vendor-specific compatible, among:
+
+- "amlogic,meson-g12a-mali"
+  Required properties:
+  - resets : Should contain phandles of :
+    + GPU reset line
+    + GPU APB glue reset line
+
+Example for a Mali-G31:
+
+gpu@ffa30000 {
+       compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
+       reg = <0xffe40000 0x10000>;
+       interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+       interrupt-names = "job", "mmu", "gpu";
+       clocks = <&clk CLKID_MALI>;
+       mali-supply = <&vdd_gpu>;
+       operating-points-v2 = <&gpu_opp_table>;
+       resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
+};
+
+gpu_opp_table: opp_table0 {
+       compatible = "operating-points-v2";
+
+       opp@533000000 {
+               opp-hz = /bits/ 64 <533000000>;
+               opp-microvolt = <1250000>;
+       };
+       opp@450000000 {
+               opp-hz = /bits/ 64 <450000000>;
+               opp-microvolt = <1150000>;
+       };
+       opp@400000000 {
+               opp-hz = /bits/ 64 <400000000>;
+               opp-microvolt = <1125000>;
+       };
+       opp@350000000 {
+               opp-hz = /bits/ 64 <350000000>;
+               opp-microvolt = <1075000>;
+       };
+       opp@266000000 {
+               opp-hz = /bits/ 64 <266000000>;
+               opp-microvolt = <1025000>;
+       };
+       opp@160000000 {
+               opp-hz = /bits/ 64 <160000000>;
+               opp-microvolt = <925000>;
+       };
+       opp@100000000 {
+               opp-hz = /bits/ 64 <100000000>;
+               opp-microvolt = <912500>;
+       };
+};