spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi

Move the Documentation/devicetree/bindings/mtd/cadence-quadspi.txt to
Documentation/devicetree/bindings/spi/

Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201124041840.31066-5-vadivel.muruganx.ramuthevar@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
deleted file mode 100644 (file)
index 945be7d..0000000
--- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-* Cadence Quad SPI controller
-
-Required properties:
-- compatible : should be one of the following:
-       Generic default - "cdns,qspi-nor".
-       For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
-       For TI AM654 SoC  - "ti,am654-ospi", "cdns,qspi-nor".
-- reg : Contains two entries, each of which is a tuple consisting of a
-       physical address and length. The first entry is the address and
-       length of the controller register set. The second entry is the
-       address and length of the QSPI Controller data area.
-- interrupts : Unit interrupt specifier for the controller interrupt.
-- clocks : phandle to the Quad SPI clock.
-- cdns,fifo-depth : Size of the data FIFO in words.
-- cdns,fifo-width : Bus width of the data FIFO in bytes.
-- cdns,trigger-address : 32-bit indirect AHB trigger address.
-
-Optional properties:
-- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
-- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
-  the read data rather than the QSPI clock. Make sure that QSPI return
-  clock is populated on the board before using this property.
-
-Optional subnodes:
-Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
-custom properties:
-- cdns,read-delay : Delay for read capture logic, in clock cycles
-- cdns,tshsl-ns : Delay in nanoseconds for the length that the master
-                  mode chip select outputs are de-asserted between
-                 transactions.
-- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being
-                  de-activated and the activation of another.
-- cdns,tchsh-ns : Delay in nanoseconds between last bit of current
-                  transaction and deasserting the device chip select
-                 (qspi_n_ss_out).
-- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low
-                  and first bit transfer.
-- resets       : Must contain an entry for each entry in reset-names.
-                 See ../reset/reset.txt for details.
-- reset-names  : Must include either "qspi" and/or "qspi-ocp".
-
-Example:
-
-       qspi: spi@ff705000 {
-               compatible = "cdns,qspi-nor";
-               #address-cells = <1>;
-               #size-cells = <0>;
-               reg = <0xff705000 0x1000>,
-                     <0xffa00000 0x1000>;
-               interrupts = <0 151 4>;
-               clocks = <&qspi_clk>;
-               cdns,is-decoded-cs;
-               cdns,fifo-depth = <128>;
-               cdns,fifo-width = <4>;
-               cdns,trigger-address = <0x00000000>;
-               resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
-               reset-names = "qspi", "qspi-ocp";
-
-               flash0: n25q00@0 {
-                       ...
-                       cdns,read-delay = <4>;
-                       cdns,tshsl-ns = <50>;
-                       cdns,tsd2d-ns = <50>;
-                       cdns,tchsh-ns = <4>;
-                       cdns,tslch-ns = <4>;
-               };
-       };

diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
new file mode 100644 (file)
index 0000000..945be7d
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
@@ -0,0 +1,67 @@
+* Cadence Quad SPI controller
+
+Required properties:
+- compatible : should be one of the following:
+       Generic default - "cdns,qspi-nor".
+       For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
+       For TI AM654 SoC  - "ti,am654-ospi", "cdns,qspi-nor".
+- reg : Contains two entries, each of which is a tuple consisting of a
+       physical address and length. The first entry is the address and
+       length of the controller register set. The second entry is the
+       address and length of the QSPI Controller data area.
+- interrupts : Unit interrupt specifier for the controller interrupt.
+- clocks : phandle to the Quad SPI clock.
+- cdns,fifo-depth : Size of the data FIFO in words.
+- cdns,fifo-width : Bus width of the data FIFO in bytes.
+- cdns,trigger-address : 32-bit indirect AHB trigger address.
+
+Optional properties:
+- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
+- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
+  the read data rather than the QSPI clock. Make sure that QSPI return
+  clock is populated on the board before using this property.
+
+Optional subnodes:
+Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
+custom properties:
+- cdns,read-delay : Delay for read capture logic, in clock cycles
+- cdns,tshsl-ns : Delay in nanoseconds for the length that the master
+                  mode chip select outputs are de-asserted between
+                 transactions.
+- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being
+                  de-activated and the activation of another.
+- cdns,tchsh-ns : Delay in nanoseconds between last bit of current
+                  transaction and deasserting the device chip select
+                 (qspi_n_ss_out).
+- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low
+                  and first bit transfer.
+- resets       : Must contain an entry for each entry in reset-names.
+                 See ../reset/reset.txt for details.
+- reset-names  : Must include either "qspi" and/or "qspi-ocp".
+
+Example:
+
+       qspi: spi@ff705000 {
+               compatible = "cdns,qspi-nor";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0xff705000 0x1000>,
+                     <0xffa00000 0x1000>;
+               interrupts = <0 151 4>;
+               clocks = <&qspi_clk>;
+               cdns,is-decoded-cs;
+               cdns,fifo-depth = <128>;
+               cdns,fifo-width = <4>;
+               cdns,trigger-address = <0x00000000>;
+               resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
+               reset-names = "qspi", "qspi-ocp";
+
+               flash0: n25q00@0 {
+                       ...
+                       cdns,read-delay = <4>;
+                       cdns,tshsl-ns = <50>;
+                       cdns,tsd2d-ns = <50>;
+                       cdns,tchsh-ns = <4>;
+                       cdns,tslch-ns = <4>;
+               };
+       };