list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
- val = snd_soc_component_read32(component,
+ val = snd_soc_component_read(component,
WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
* is connected
*/
for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
- cfg0 = snd_soc_component_read32(comp,
+ cfg0 = snd_soc_component_read(comp,
WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j));
- cfg1 = snd_soc_component_read32(comp,
+ cfg1 = snd_soc_component_read(comp,
WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j));
inp0_sel = cfg0 &
return -EINVAL;
}
- tx_mux_sel = snd_soc_component_read32(comp, tx_port_reg) &
+ tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
(shift_val << shift);
tx_mux_sel = tx_mux_sel >> shift;
if (adc_mux_n < 4) {
reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n;
mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n;
- mux_sel = snd_soc_component_read32(comp, reg) & 0x3;
+ mux_sel = snd_soc_component_read(comp, reg) & 0x3;
} else {
reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4;
mreg = reg;
- mux_sel = snd_soc_component_read32(comp, reg) >> 6;
+ mux_sel = snd_soc_component_read(comp, reg) >> 6;
}
if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC)
return 0;
- return snd_soc_component_read32(comp, mreg) & 0x07;
+ return snd_soc_component_read(comp, mreg) & 0x07;
}
static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
amic_n);
if (pwr_level_reg) {
- switch ((snd_soc_component_read32(comp, pwr_level_reg) &
+ switch ((snd_soc_component_read(comp, pwr_level_reg) &
WCD9335_AMIC_PWR_LVL_MASK) >>
WCD9335_AMIC_PWR_LVL_SHIFT) {
case WCD9335_AMIC_PWR_LEVEL_LP:
break;
}
}
- hpf_coff_freq = (snd_soc_component_read32(comp, dec_cfg_reg) &
+ hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
if (hpf_coff_freq != CF_MIN_3DB_150HZ)
snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
0x10, 0x00);
snd_soc_component_write(comp, tx_gain_ctl_reg,
- snd_soc_component_read32(comp, tx_gain_ctl_reg));
+ snd_soc_component_read(comp, tx_gain_ctl_reg));
break;
case SND_SOC_DAPM_PRE_PMD:
- hpf_coff_freq = (snd_soc_component_read32(comp, dec_cfg_reg) &
+ hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10);
snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
- val = snd_soc_component_read32(comp, gain_reg);
+ val = snd_soc_component_read(comp, gain_reg);
val += offset_val;
snd_soc_component_write(comp, gain_reg, val);
break;
}
if ((reg != prim_int_reg) &&
- ((snd_soc_component_read32(comp, prim_int_reg)) &
+ ((snd_soc_component_read(comp, prim_int_reg)) &
WCD9335_CDC_RX_PGA_MUTE_EN_MASK))
snd_soc_component_update_bits(comp, reg,
WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
break;
case SND_SOC_DAPM_POST_PMU:
wcd9335_config_compander(comp, w->shift, event);
- val = snd_soc_component_read32(comp, gain_reg);
+ val = snd_soc_component_read(comp, gain_reg);
val += offset_val;
snd_soc_component_write(comp, gain_reg, val);
break;
u8 hph_pa_status;
bool is_hphl_pa, is_hphr_pa;
- hph_pa_status = snd_soc_component_read32(component, WCD9335_ANA_HPH);
+ hph_pa_status = snd_soc_component_read(component, WCD9335_ANA_HPH);
is_hphl_pa = hph_pa_status >> 7;
is_hphr_pa = (hph_pa_status & 0x40) >> 6;
- hph_l_en = snd_soc_component_read32(component, WCD9335_HPH_L_EN);
- hph_r_en = snd_soc_component_read32(component, WCD9335_HPH_R_EN);
+ hph_l_en = snd_soc_component_read(component, WCD9335_HPH_L_EN);
+ hph_r_en = snd_soc_component_read(component, WCD9335_HPH_R_EN);
l_val = (hph_l_en & 0xC0) | 0x20 | gain;
r_val = (hph_r_en & 0xC0) | 0x20 | gain;
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Read DEM INP Select */
- dem_inp = snd_soc_component_read32(comp,
+ dem_inp = snd_soc_component_read(comp,
WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03;
if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
(hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
case SND_SOC_DAPM_PRE_PMU:
/* Read DEM INP Select */
- dem_inp = snd_soc_component_read32(comp,
+ dem_inp = snd_soc_component_read(comp,
WCD9335_CDC_RX2_RX_PATH_SEC0) &
WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK;
if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
WCD9335_CDC_RX_PGA_MUTE_DISABLE);
/* Remove mix path mute if it is enabled */
- if ((snd_soc_component_read32(comp,
+ if ((snd_soc_component_read(comp,
WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) &
WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
snd_soc_component_update_bits(comp,
WCD9335_CDC_RX_PGA_MUTE_DISABLE);
/* Remove mix path mute if it is enabled */
- if ((snd_soc_component_read32(comp, mix_vol_reg)) &
+ if ((snd_soc_component_read(comp, mix_vol_reg)) &
WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
snd_soc_component_update_bits(comp, mix_vol_reg,
WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
WCD9335_CDC_RX_PGA_MUTE_DISABLE);
/* Remove mix path mute if it is enabled */
- if ((snd_soc_component_read32(comp,
+ if ((snd_soc_component_read(comp,
WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) &
WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
snd_soc_component_update_bits(comp,
WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
WCD9335_CDC_RX_PGA_MUTE_DISABLE);
/* Remove mix path mute if it is enabled */
- if ((snd_soc_component_read32(comp,
+ if ((snd_soc_component_read(comp,
WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) &
WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
snd_soc_component_update_bits(comp,
*/
usleep_range(5000, 5500);
- if (!(snd_soc_component_read32(comp,
+ if (!(snd_soc_component_read(comp,
WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) &
WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK))
WARN(1, "%s: Efuse sense is not complete\n", __func__);
if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
continue;
- cfg0 = snd_soc_component_read32(comp,
+ cfg0 = snd_soc_component_read(comp,
WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j));
- cfg1 = snd_soc_component_read32(comp,
+ cfg1 = snd_soc_component_read(comp,
WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j));
inp0_sel = cfg0 &
/* Interpolators 5 and 6 are not aviliable in Tavil */
if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
continue;
- val = snd_soc_component_read32(component,
+ val = snd_soc_component_read(component,
WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
return -EINVAL;
}
- tx_mux_sel = snd_soc_component_read32(comp, tx_port_reg) &
+ tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
(shift_val << shift);
tx_mux_sel = tx_mux_sel >> shift;
((band_idx * BAND_MAX + coeff_idx) *
sizeof(uint32_t)) & 0x7F);
- value |= snd_soc_component_read32(component, b2_reg);
+ value |= snd_soc_component_read(component, b2_reg);
snd_soc_component_write(component, reg,
((band_idx * BAND_MAX + coeff_idx)
* sizeof(uint32_t) + 1) & 0x7F);
- value |= (snd_soc_component_read32(component, b2_reg) << 8);
+ value |= (snd_soc_component_read(component, b2_reg) << 8);
snd_soc_component_write(component, reg,
((band_idx * BAND_MAX + coeff_idx)
* sizeof(uint32_t) + 2) & 0x7F);
- value |= (snd_soc_component_read32(component, b2_reg) << 16);
+ value |= (snd_soc_component_read(component, b2_reg) << 16);
snd_soc_component_write(component, reg,
((band_idx * BAND_MAX + coeff_idx)
* sizeof(uint32_t) + 3) & 0x7F);
/* Mask bits top 2 bits since they are reserved */
- value |= (snd_soc_component_read32(component, b2_reg) << 24);
+ value |= (snd_soc_component_read(component, b2_reg) << 24);
return value;
}
break;
case SND_SOC_DAPM_POST_PMU:
- val = snd_soc_component_read32(comp, gain_reg);
+ val = snd_soc_component_read(comp, gain_reg);
val += offset_val;
snd_soc_component_write(comp, gain_reg, val);
break;
case SND_SOC_DAPM_POST_PMU:
/* B1 GAIN */
snd_soc_component_write(comp, reg,
- snd_soc_component_read32(comp, reg));
+ snd_soc_component_read(comp, reg));
/* B2 GAIN */
reg++;
snd_soc_component_write(comp, reg,
- snd_soc_component_read32(comp, reg));
+ snd_soc_component_read(comp, reg));
/* B3 GAIN */
reg++;
snd_soc_component_write(comp, reg,
- snd_soc_component_read32(comp, reg));
+ snd_soc_component_read(comp, reg));
/* B4 GAIN */
reg++;
snd_soc_component_write(comp, reg,
- snd_soc_component_read32(comp, reg));
+ snd_soc_component_read(comp, reg));
/* B5 GAIN */
reg++;
snd_soc_component_write(comp, reg,
- snd_soc_component_read32(comp, reg));
+ snd_soc_component_read(comp, reg));
break;
default:
break;
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_component_write(comp, gain_reg,
- snd_soc_component_read32(comp, gain_reg));
+ snd_soc_component_read(comp, gain_reg));
break;
}
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
/* Read DEM INP Select */
- dem_inp = snd_soc_component_read32(comp,
+ dem_inp = snd_soc_component_read(comp,
WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03;
if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
switch (event) {
case SND_SOC_DAPM_PRE_PMU:
- dem_inp = snd_soc_component_read32(comp,
+ dem_inp = snd_soc_component_read(comp,
WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03;
if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
(hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
/* Remove mix path mute if it is enabled */
- if ((snd_soc_component_read32(comp,
+ if ((snd_soc_component_read(comp,
WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10)
snd_soc_component_update_bits(comp,
WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
++adc_mux_index;
continue;
}
- adc_mux_sel = ((snd_soc_component_read32(comp, adc_mux_ctl_reg)
+ adc_mux_sel = ((snd_soc_component_read(comp, adc_mux_ctl_reg)
& 0xF8) >> 3) - 1;
if (adc_mux_sel == dmic) {
if (dec_found && adc_mux_index <= 8) {
tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index);
- tx_stream_fs = snd_soc_component_read32(comp, tx_fs_reg) & 0x0F;
+ tx_stream_fs = snd_soc_component_read(comp, tx_fs_reg) & 0x0F;
if (tx_stream_fs <= 4) {
if (wcd->dmic_sample_rate <=
WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ)
adc_mux_n - 4;
}
- is_amic = (((snd_soc_component_read32(comp, adc_mux_in_reg)
+ is_amic = (((snd_soc_component_read(comp, adc_mux_in_reg)
& mask) >> shift) == 1);
if (!is_amic)
return 0;
- return snd_soc_component_read32(comp, amic_mux_sel_reg) & 0x07;
+ return snd_soc_component_read(comp, amic_mux_sel_reg) & 0x07;
}
static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
if (!pwr_level_reg)
break;
- switch ((snd_soc_component_read32(comp, pwr_level_reg) &
+ switch ((snd_soc_component_read(comp, pwr_level_reg) &
WCD934X_AMIC_PWR_LVL_MASK) >>
WCD934X_AMIC_PWR_LVL_SHIFT) {
case WCD934X_AMIC_PWR_LEVEL_LP:
}
break;
case SND_SOC_DAPM_POST_PMU:
- hpf_coff_freq = (snd_soc_component_read32(comp, dec_cfg_reg) &
+ hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
snd_soc_component_update_bits(comp, dec_cfg_reg,
}
/* apply gain after decimator is enabled */
snd_soc_component_write(comp, tx_gain_ctl_reg,
- snd_soc_component_read32(comp,
+ snd_soc_component_read(comp,
tx_gain_ctl_reg));
break;
case SND_SOC_DAPM_PRE_PMD:
- hpf_coff_freq = (snd_soc_component_read32(comp, dec_cfg_reg) &
+ hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
if (hpf_coff_freq != CF_MIN_3DB_150HZ) {